Matching Items (120)
Description
ABSTRACT Developing new non-traditional device models is gaining popularity as the silicon-based electrical device approaches its limitation when it scales down. Membrane systems, also called P systems, are a new class of biological computation model inspired by the way cells process chemical signals. Spiking Neural P systems (SNP systems), a certain kind of membrane systems, is inspired by the way the neurons in brain interact using electrical spikes. Compared to the traditional Boolean logic, SNP systems not only perform similar functions but also provide a more promising solution for reliable computation. Two basic neuron types, Low Pass (LP) neurons and High Pass (HP) neurons, are introduced. These two basic types of neurons are capable to build an arbitrary SNP neuron. This leads to the conclusion that these two basic neuron types are Turing complete since SNP systems has been proved Turing complete. These two basic types of neurons are further used as the elements to construct general-purpose arithmetic circuits, such as adder, subtractor and comparator. In this thesis, erroneous behaviors of neurons are discussed. Transmission error (spike loss) is proved to be equivalent to threshold error, which makes threshold error discussion more universal. To improve the reliability, a new structure called motif is proposed. Compared to Triple Modular Redundancy improvement, motif design presents its efficiency and effectiveness in both single neuron and arithmetic circuit analysis. DRAM-based CMOS circuits are used to implement the two basic types of neurons. Functionality of basic type neurons is proved using the SPICE simulations. The motif improved adder and the comparator, as compared to conventional Boolean logic design, are much more reliable with lower leakage, and smaller silicon area. This leads to the conclusion that SNP system could provide a more promising solution for reliable computation than the conventional Boolean logic.
ContributorsAn, Pei (Author) / Cao, Yu (Thesis advisor) / Barnaby, Hugh (Committee member) / Chakrabarti, Chaitali (Committee member) / Arizona State University (Publisher)
Created2013
Description
This dissertation is on the study of structural and optical properties of some III-V and II-VI compound semiconductors. The first part of this dissertation is a study of the deformation mechanisms associated with nanoindentation and nanoscratching of InP, GaN, and ZnO crystals. The second part is an investigation of some fundamental issues regarding compositional fluctuations and microstructure in GaInNAs and InAlN alloys. In the first part, the microstructure of (001) InP scratched in an atomic force microscope with a small diamond tip has been studied as a function of applied normal force and crystalline direction in order to understand at the nanometer scale the deformation mechanisms in the zinc-blende structure. TEM images show deeper dislocation propagation for scratches along <110> compared to <100>. High strain fields were observed in <100> scratches, indicating hardening due to locking of dislocations gliding on different slip planes. Reverse plastic flow have been observed in <110> scratches in the form of pop-up events that result from recovery of stored elastic strain. In a separate study, nanoindentation-induced plastic deformation has been studied in c-, a-, and m-plane ZnO single crystals and c-plane GaN respectively, to study the deformation mechanism in wurtzite hexagonal structures. TEM results reveal that the prime deformation mechanism is slip on basal planes and in some cases, on pyramidal planes, and strain built up along particular directions. No evidence of phase transformation or cracking was observed in both materials. CL imaging reveals quenching of near band-edge emission by dislocations. In the second part, compositional inhomogeneity in quaternary GaInNAs and ternary InAlN alloys has been studied using TEM. It is shown that exposure to antimony during growth of GaInNAs results in uniform chemical composition in the epilayer, as antimony suppresses the surface mobility of adatoms that otherwise leads to two-dimensional growth and elemental segregation. In a separate study, compositional instability is observed in lattice-matched InAlN films grown on GaN, for growth beyond a certain thickness. Beyond 200 nm of thickness, two sub-layers with different indium content are observed, the top one with lower indium content.
ContributorsHuang, Jingyi (Author) / Ponce, Fernando A. (Thesis advisor) / Carpenter, Ray W (Committee member) / Smith, David J. (Committee member) / Yu, Hongbin (Committee member) / Treacy, Michael Mj (Committee member) / Arizona State University (Publisher)
Created2013
Description
The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-Silicon bugs, minimizing design risk and cost. The unique features of the approach include 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; 3) compensation of AC performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45nm node that can map AMS modules across 22nm to 90nm technology nodes. A systematic emulation approach to map any analog transistor to PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 90nm nodes with less than a 5% error. Voltage-controlled delay lines at 65nm and 90nm are emulated by 32nm PANDA, which successfully match important analog metrics. And at-speed emulation is achieved as well. Several other 90nm analog blocks are successfully emulated by the 45nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H)
ContributorsXu, Cheng (Author) / Cao, Yu (Thesis advisor) / Blain Christen, Jennifer (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2012
Description
Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological difficulties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation. Non-classical multiple-gate structures such as double-gate (DG) FinFETs and surrounding gate field-effect-transistors (SGFETs) have good electrostatic integrity and are an alternative to planar MOSFETs for below 20 nm technology nodes. Circuit design with these devices need compact models for SPICE simulation. In this work physics based compact models for the common-gate symmetric DG-FinFET, independent-gate asymmetric DG-FinFET, and SGFET are developed. Despite the complex device structure and boundary conditions for the Poisson-Boltzmann equation, the core structure of the DG-FinFET and SGFET models, are maintained similar to the surface potential based compact models for planar MOSFETs such as SP and PSP. TCAD simulations show differences between the transient behavior and the capacitance-voltage characteristics of bulk and SOI FinFETs if the gate-voltage swing includes the accumulation region. This effect can be captured by a compact model of FinFETs only if it includes the contribution of both types of carriers in the Poisson-Boltzmann equation. An accurate implicit input voltage equation valid in all regions of operation is proposed for common-gate symmetric DG-FinFETs with intrinsic or lightly doped bodies. A closed-form algorithm is developed for solving the new input voltage equation including ambipolar effects. The algorithm is verified for both the surface potential and its derivatives and includes a previously published analytical approximation for surface potential as a special case when ambipolar effects can be neglected. The symmetric linearization method for common-gate symmetric DG-FinFETs is developed in a form free of the charge-sheet approximation present in its original formulation for bulk MOSFETs. The accuracy of the proposed technique is verified by comparison with exact results. An alternative and computationally efficient description of the boundary between the trigonometric and hyperbolic solutions of the Poisson-Boltzmann equation for the independent-gate asymmetric DG-FinFET is developed in terms of the Lambert W function. Efficient numerical algorithm is proposed for solving the input voltage equation. Analytical expressions for terminal charges of an independent-gate asymmetric DG-FinFET are derived. The new charge model is C-infinity continuous, valid for weak as well as for strong inversion condition of both the channels and does not involve the charge-sheet approximation. This is accomplished by developing the symmetric linearization method in a form that does not require identical boundary conditions at the two Si-SiO2 interfaces and allows for volume inversion in the DG-FinFET. Verification of the model is performed with both numerical computations and 2D TCAD simulations under a wide range of biasing conditions. The model is implemented in a standard circuit simulator through Verilog-A code. Simulation examples for both digital and analog circuits verify good model convergence and demonstrate the capabilities of new circuit topologies that can be implemented using independent-gate asymmetric DG-FinFETs.
ContributorsDessai, Gajanan (Author) / Gildenblat, Gennady (Committee member) / McAndrew, Colin (Committee member) / Cao, Yu (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
Description
High electron mobility transistors (HEMTs) based on Group III-nitride heterostructures have been characterized by advanced electron microscopy methods including off-axis electron holography, nanoscale chemical analysis, and electrical measurements, as well as other techniques. The dissertation was organized primarily into three topical areas: (1) characterization of near-gate defects in electrically stressed AlGaN/GaN HEMTs, (2) microstructural and chemical analysis of the gate/buffer interface of AlN/GaN HEMTs, and (3) studies of the impact of laser-liftoff processing on AlGaN/GaN HEMTs. The electrical performance of stressed AlGaN/GaN HEMTs was measured and the devices binned accordingly. Source- and drain-side degraded, undegraded, and unstressed devices were then prepared via focused-ion-beam milling for examination. Defects in the near-gate region were identified and their correlation to electrical measurements analyzed. Increased gate leakage after electrical stressing is typically attributed to "V"-shaped defects at the gate edge. However, strong evidence was found for gate metal diffusion into the barrier layer as another contributing factor. AlN/GaN HEMTs grown on sapphire substrates were found to have high electrical performance which is attributed to the AlN barrier layer, and robust ohmic and gate contact processes. TEM analysis identified oxidation at the gate metal/AlN buffer layer interface. This thin a-oxide gate insulator was further characterized by energy-dispersive x-ray spectroscopy and energy-filtered TEM. Attributed to this previously unidentified layer, high reverse gate bias up to −30 V was demonstrated and drain-induced gate leakage was suppressed to values of less than 10−6 A/mm. In addition, extrinsic gm and ft * LG were improved to the highest reported values for AlN/GaN HEMTs fabricated on sapphire substrates. Laser-liftoff (LLO) processing was used to separate the active layers from sapphire substrates for several GaN-based HEMT devices, including AlGaN/GaN and InAlN/GaN heterostructures. Warpage of the LLO samples resulted from relaxation of the as-grown strain and strain arising from dielectric and metal depositions, and this strain was quantified by both Newton's rings and Raman spectroscopy methods. TEM analysis demonstrated that the LLO processing produced no detrimental effects on the quality of the epitaxial layers. TEM micrographs showed no evidence of either damage to the ~2 μm GaN epilayer generated threading defects.
ContributorsJohnson, Michael R. (Author) / Mccartney, Martha R (Thesis advisor) / Smith, David J. (Committee member) / Goodnick, Stephen (Committee member) / Shumway, John (Committee member) / Chen, Tingyong (Committee member) / Arizona State University (Publisher)
Created2012
Description
Test cost has become a significant portion of device cost and a bottleneck in high volume manufacturing. Increasing integration density and shrinking feature sizes increased test time/cost and reduce observability. Test engineers have to put a tremendous effort in order to maintain test cost within an acceptable budget. Unfortunately, there is not a single straightforward solution to the problem. Products that are tested have several application domains and distinct customer profiles. Some products are required to operate for long periods of time while others are required to be low cost and optimized for low cost. Multitude of constraints and goals make it impossible to find a single solution that work for all cases. Hence, test development/optimization is typically design/circuit dependent and even process specific. Therefore, test optimization cannot be performed using a single test approach, but necessitates a diversity of approaches. This works aims at addressing test cost minimization and test quality improvement at various levels. In the first chapter of the work, we investigate pre-silicon strategies, such as design for test and pre-silicon statistical simulation optimization. In the second chapter, we investigate efficient post-silicon test strategies, such as adaptive test, adaptive multi-site test, outlier analysis, and process shift detection/tracking.
ContributorsYilmaz, Ender (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
Description
HgCdTe is currently the dominant material for infrared sensing and imaging, and is usually grown on lattice-matched bulk CdZnTe (CZT) substrates. There have been significant recent efforts to identify alternative substrates to CZT as well as alternative detector materials to HgCdTe. In this dissertation research, a wide range of transmission electron microscopy (TEM) imaging and analytical techniques was used in the characterization of epitaxial HgCdTe and related materials and substrates for third generation IR detectors. ZnTe layers grown on Si substrates are considered to be promising candidates for lattice-matched, large-area, and low-cost composite substrates for deposition of II-VI and III-V compound semiconductors with lattice constants near 6.1 Å. After optimizing MBE growth conditions including substrate pretreatment prior to film growth, as well as nucleation and growth temperatures, thick ZnTe/Si films with high crystallinity, low defect density, and excellent surface morphology were achieved. Changes in the Zn/Te flux ratio used during growth were also investigated. Small-probe microanalysis confirmed that a small amount of As was present at the ZnTe/Si interface. A microstructural study of HgCdTe/CdTe/GaAs (211)B and CdTe/GaAs (211)B heterostructures grown using MBE was carried out. High quality MBE-grown CdTe on GaAs(211)B substrates was demonstrated to be a viable composite substrate platform for HgCdTe growth. In addition, analysis of interfacial misfit dislocations and residual strain showed that the CdTe/GaAs interface was fully relaxed. In the case of HgCdTe/CdTe/ GaAs(211)B, thin HgTe buffer layers between HgCdTe and CdTe were also investigated for improving the HgCdTe crystal quality. A set of ZnTe layers epitaxially grown on GaSb(211)B substrates using MBE was studied using high resolution X-ray diffraction (HRXRD) measurements and TEM characterization in order to investigate conditions for defect-free growth. HRXRD results gave critical thickness estimates between 350 nm and 375 nm, in good agreement with theoretical predictions. Moreover, TEM results confirmed that ZnTe layers with thicknesses of 350 nm had highly coherent interfaces and very low dislocation densities, unlike samples with the thicker ZnTe layers.
ContributorsKim, Jae Jin (Author) / Smith, David J. (Thesis advisor) / McCartney, Martha R. (Committee member) / Alford, Terry L. (Committee member) / Crozier, Peter A. (Committee member) / Arizona State University (Publisher)
Created2012
Description
Memories play an integral role in today's advanced ICs. Technology scaling has enabled high density designs at the price paid for impact due to variability and reliability. It is imperative to have accurate methods to measure and extract the variability in the SRAM cell to produce accurate reliability projections for future technologies. This work presents a novel test measurement and extraction technique which is non-invasive to the actual operation of the SRAM memory array. The salient features of this work include i) A single ended SRAM test structure with no disturbance to SRAM operations ii) a convenient test procedure that only requires quasi-static control of external voltages iii) non-iterative method that extracts the VTH variation of each transistor from eight independent switch point measurements. With the present day technology scaling, in addition to the variability with the process, there is also the impact of other aging mechanisms which become dominant. The various aging mechanisms like Negative Bias Temperature Instability (NBTI), Channel Hot Carrier (CHC) and Time Dependent Dielectric Breakdown (TDDB) are critical in the present day nano-scale technology nodes. In this work, we focus on the impact of NBTI due to aging in the SRAM cell and have used Trapping/De-Trapping theory based log(t) model to explain the shift in threshold voltage VTH. The aging section focuses on the following i) Impact of Statistical aging in PMOS device due to NBTI dominates the temporal shift of SRAM cell ii) Besides static variations , shifting in VTH demands increased guard-banding margins in design stage iii) Aging statistics remain constant during the shift, presenting a secondary effect in aging prediction. iv) We have investigated to see if the aging mechanism can be used as a compensation technique to reduce mismatch due to process variations. Finally, the entire test setup has been tested in SPICE and also validated with silicon and the results are presented. The method also facilitates the study of design metrics such as static, read and write noise margins and also the data retention voltage and thus help designers to improve the cell stability of SRAM.
ContributorsRavi, Venkatesa (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Clark, Lawrence (Committee member) / Arizona State University (Publisher)
Created2013
Description
Non-volatile memories (NVM) are widely used in modern electronic devices due to their non-volatility, low static power consumption and high storage density. While Flash memories are the dominant NVM technology, resistive memories such as phase change access memory (PRAM) and spin torque transfer random access memory (STT-MRAM) are gaining ground. All these technologies suffer from reliability degradation due to process variations, structural limits and material property shift. To address the reliability concerns of these NVM technologies, multi-level low cost solutions are proposed for each of them. My approach consists of first building a comprehensive error model. Next the error characteristics are exploited to develop low cost multi-level strategies to compensate for the errors. For instance, for NAND Flash memory, I first characterize errors due to threshold voltage variations as a function of the number of program/erase cycles. Next a flexible product code is designed to migrate to a stronger ECC scheme as program/erase cycles increases. An adaptive data refresh scheme is also proposed to improve memory reliability with low energy cost for applications with different data update frequencies. For PRAM, soft errors and hard errors models are built based on shifts in the resistance distributions. Next I developed a multi-level error control approach involving bit interleaving and subblock flipping at the architecture level, threshold resistance tuning at the circuit level and programming current profile tuning at the device level. This approach helped reduce the error rate significantly so that it was now sufficient to use a low cost ECC scheme to satisfy the memory reliability constraint. I also studied the reliability of a PRAM+DRAM hybrid memory system and analyzed the tradeoffs between memory performance, programming energy and lifetime. For STT-MRAM, I first developed an error model based on process variations. I developed a multi-level approach to reduce the error rates that consisted of increasing the W/L ratio of the access transistor, increasing the voltage difference across the memory cell and adjusting the current profile during write operation. This approach enabled use of a low cost BCH based ECC scheme to achieve very low block failure rates.
ContributorsYang, Chengen (Author) / Chakrabarti, Chaitali (Thesis advisor) / Cao, Yu (Committee member) / Ogras, Umit Y. (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2014
Description
With increasing demand for System on Chip (SoC) and System in Package (SiP) design in computer and communication technologies, integrated inductor which is an essential passive component has been widely used in numerous integrated circuits (ICs) such as in voltage regulators and RF circuits. In this work, soft ferromagnetic core material, amorphous Co-Zr-Ta-B, was incorporated into on-chip and in-package inductors in order to scale down inductors and improve inductors performance in both inductance density and quality factor. With two layers of 500 nm Co-Zr-Ta-B films a 3.5X increase in inductance and a 3.9X increase in quality factor over inductors without magnetic films were measured at frequencies as high as 1 GHz. By laminating technology, up to 9.1X increase in inductance and more than 5X increase in quality factor (Q) were obtained from stripline inductors incorporated with 50 nm by 10 laminated films with a peak Q at 300 MHz. It was also demonstrated that this peak Q can be pushed towards high frequency as far as 1GHz by a combination of patterning magnetic films into fine bars and laminations. The role of magnetic vias in magnetic flux and eddy current control was investigated by both simulation and experiment using different patterning techniques and by altering the magnetic via width. Finger-shaped magnetic vias were designed and integrated into on-chip RF inductors improving the frequency of peak quality factor from 400 MHz to 800 MHz without sacrificing inductance enhancement. Eddy current and magnetic flux density in different areas of magnetic vias were analyzed by HFSS 3D EM simulation. With optimized magnetic vias, high frequency response of up to 2 GHz was achieved. Furthermore, the effect of applied magnetic field on on-chip inductors was investigated for high power applications. It was observed that as applied magnetic field along the hard axis (HA) increases, inductance maintains similar value initially at low fields, but decreases at larger fields until the magnetic films become saturated. The high frequency quality factor showed an opposite trend which is correlated to the reduction of ferromagnetic resonant absorption in the magnetic film. In addition, experiments showed that this field-dependent inductance change varied with different patterned magnetic film structures, including bars/slots and fingers structures. Magnetic properties of Co-Zr-Ta-B films on standard organic package substrates including ABF and polyimide were also characterized. Effects of substrate roughness and stress were analyzed and simulated which provide strategies for integrating Co-Zr-Ta-B into package inductors and improving inductors performance. Stripline and spiral inductors with Co-Zr-Ta-B films were fabricated on both ABF and polyimide substrates. Maximum 90% inductance increase in hundreds MHz frequency range were achieved in stripline inductors which are suitable for power delivery applications. Spiral inductors with Co-Zr-Ta-B films showed 18% inductance increase with quality factor of 4 at frequency up to 3 GHz.
ContributorsWu, Hao (Author) / Yu, Hongbin (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Chickamenahalli, Shamala (Committee member) / Arizona State University (Publisher)
Created2013