Matching Items (232)
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Description
The recent emergence of DNA-based diagnostics increases the demand for rapid DNA sequencing technologies. One method to achieve this is to pass DNA through a nanopore, recording the trans-membrane current with a low-noise current amplifier. The project outlined in this report aims to demonstrate a design of a custom amplifier

The recent emergence of DNA-based diagnostics increases the demand for rapid DNA sequencing technologies. One method to achieve this is to pass DNA through a nanopore, recording the trans-membrane current with a low-noise current amplifier. The project outlined in this report aims to demonstrate a design of a custom amplifier that offers a wider bandwidth than current designs while maintaining a low signal to noise ratio. The novel amplifier has been designed such that a multi-stage RF signal chain is integrated with an existing amplifier circuit to achieve DNA translocation. Both the existing amplifier circuit and the RF signal chain have produced outputs showing that the two amplifiers are functional and both low frequency signals and high frequency signals can be amplified with this comprehensive circuit design.
ContributorsDharan, Abhishek (Co-author) / Becker, Jared (Co-author) / Goryll, Michael (Thesis director) / Yu, Hongyu (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2014-05
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Description
Electrospun nanofibers can be prepared from various kinds of inorganic substances by electro-spinning techniques. They have great potential in many applications including super capacitors, lithium ion batteries, filtration, catalyst and enzyme carriers, and sensors [1]. The traditional way to produce electrospun nanofibers is needle based electro-spinning [1]. However, electrospun nanofibers

Electrospun nanofibers can be prepared from various kinds of inorganic substances by electro-spinning techniques. They have great potential in many applications including super capacitors, lithium ion batteries, filtration, catalyst and enzyme carriers, and sensors [1]. The traditional way to produce electrospun nanofibers is needle based electro-spinning [1]. However, electrospun nanofibers have not been widely used in practice because of low nanofiber production rates. One way to largely increase the electro-spinning productivity is needleless electro-spinning. In 2005, Jirsak et al. patented a rotating roller fiber generator for the mass production of nanofibers [2]. Elmarco Corporation commercialized this technique to manufacture nanofiber equipment for the production of all sorts of organic and inorganic nanofibers, and named it "NanospiderTM". For this project, my goal is to build a needleless electro-spinner to produce nanofibers as the separator of lithium ion batteries. The model of this project is based on the design of rotating roller fiber generator, and is adapted from a project at North Dakota State University in 2011 [3].
ContributorsQiao, Guanhao (Author) / Yu, Hongyu (Thesis director) / Jiang, Hanqing (Committee member) / Goryll, Michael (Committee member) / Barrett, The Honors College (Contributor) / Ira A. Fulton School of Engineering (Contributor)
Created2012-12
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Description
Head's up displays (HUD) are now emerging into the technological market that is used in various functionalities, but most of all, they are expensive. An alternative method to find cheaper ways to develop a head's up display is researched and implemented. The HUD is equipped with a processor and projector.

Head's up displays (HUD) are now emerging into the technological market that is used in various functionalities, but most of all, they are expensive. An alternative method to find cheaper ways to develop a head's up display is researched and implemented. The HUD is equipped with a processor and projector. Both of these hardware components encompasses most part of the HUD along with some manipulation of the material that the image is projected on. In this study, the software and the optics of the HUD will be explored and lastly, taking into full consideration on the future work that can be done to make improvements on the HUD.
ContributorsKim, Lilian SA (Author) / Goryll, Michael (Thesis director) / Zhang, Yong-Hang (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2014-05
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Description
The Metal Semiconductor Field Effect Transistor (MESFET) has high potential to enter analog and RF applications due to their high breakdown voltage and switching frequency characteristics. These MESFET devices could allow for high voltage analog circuits to be integrated with low voltage digital circuits on a single chip in an

The Metal Semiconductor Field Effect Transistor (MESFET) has high potential to enter analog and RF applications due to their high breakdown voltage and switching frequency characteristics. These MESFET devices could allow for high voltage analog circuits to be integrated with low voltage digital circuits on a single chip in an extremely cost effective way. Higher integration leads to electronics with increased functionality and a smaller finished product. The MESFETs are designed in-house by the research group led by Dr. Trevor Thornton. The layouts are then sent to multi-project wafer (MPW) integrated circuit foundry companies, such as the Metal Oxide Semiconductor Implementation Service (MOSIS) to be fabricated. Once returned, the electrical characteristics of the devices are measured. The MESFET has been implemented in various applications by the research group, including the low dropout linear regulator (LDO) and RF power amplifier. An advantage of the MESFET is that it can function in extreme environments such as space, allowing for complex electrical systems to continue functioning properly where traditional transistors would fail.
ContributorsKam, Jason (Author) / Thornton, Trevor (Thesis director) / Goryll, Michael (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2015-05
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Description
The existing compact models can reproduce the characteristics of MOSFETs in the temperature range of -40oC to 125oC. Some applications require circuits to operate over a wide temperature range consisting of temperatures below the specified range of existing compact models, requiring wide temperature range compact models for the design of

The existing compact models can reproduce the characteristics of MOSFETs in the temperature range of -40oC to 125oC. Some applications require circuits to operate over a wide temperature range consisting of temperatures below the specified range of existing compact models, requiring wide temperature range compact models for the design of such circuits. In order to develop wide temperature range compact models, fourteen different geometries of n-channel and p-channel MOSFETs manufactured in a 0.18μm mixed-signal process were electrically characterized over a temperature range of 40 K to 298 K. Electrical characterization included ID-VG and ID-VD under different drain, body and gate biases respectively. The effects of low-temperature operation on the performance of 0.18μm MOSFETs have been studied and discussed in terms of sub-threshold characteristics, threshold voltage, the effect of the body bias and linearity of the device. As it is well understood, the subthreshold slope, the threshold voltage, drive currents of the MOSFETs increase when the temperature of the MOSFETs is lowered, which makes it advantageous to operate the MOSFETs at low-temperatures. However the internal linearity gm1/gm3 of the MOSFETs degrades as the temperature of the MOSFETs is lowered, and the performance of the MOSFETs can be affected by the interface traps that exist in higher density close to conduction band and valence band energy levels, as the Fermi-level moves closer to bandgap edges when MOSFETs are operated at cryogenic temperatures.
ContributorsKathuria, Achal (Author) / Barnaby, Hugh (Thesis advisor) / Schroder, Dieter K. (Committee member) / Vermeire, Bert (Committee member) / Arizona State University (Publisher)
Created2010
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Description
Electronic devices are gaining an increasing market share in the medical field. Medical devices are becoming more sophisticated, and encompassing more applications. Unlike consumer electronics, medical devices have far more limitations when it comes to area, power and most importantly reliability. The medical devices industry has recently seen the advantages

Electronic devices are gaining an increasing market share in the medical field. Medical devices are becoming more sophisticated, and encompassing more applications. Unlike consumer electronics, medical devices have far more limitations when it comes to area, power and most importantly reliability. The medical devices industry has recently seen the advantages of using Flash memory instead of Read Only Memory (ROM) for firmware storage, and in some cases to replace Electrically Programmable Read Only Memories (EEPROMs) in medical devices for frequent data storage. There are direct advantages to using Flash memory instead of Read Only Memory, most importantly the fact that firmware can be rewritten along the development cycle and in the field. However, Flash technology requires high voltage circuitry that makes it harder to integrate into low power devices. There have been a lot of advances in Non-Volatile Memory (NVM) technologies, and many Flash rivals are starting to gain attention. The purpose of this thesis is to evaluate these new technologies against Flash to determine the feasibility as well as the advantages of each technology. The focus is on embedded memory in a medical device micro-controller and application specific integrated circuits (ASIC). A behavioral model of a Programmable Metallization Cell (PMC) was used to simulate the behavior and determine the advantages of using PMC technology versus flash. When compared to flash test data, PMC based embedded memory showed a reduction in power consumption by many orders of magnitude. Analysis showed that an approximated 20% device longevity increase can be achieved by using embedded PMC technology.
ContributorsHag, Eslam E (Author) / Kozicki, Michael N (Thesis advisor) / Schroder, Dieter K. (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2010
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Description
The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the

The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application.
ContributorsLepkowski, William (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2010
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Description
In this work, a high resolution analog-to-digital converter (ADC) for use in harsh environments is presented. The ADC is implemented in bulk CMOS technology and is intended for space exploration, mining and automotive applications with a range of temperature variation in excess of 250°C. A continuous time (CT) sigma delta

In this work, a high resolution analog-to-digital converter (ADC) for use in harsh environments is presented. The ADC is implemented in bulk CMOS technology and is intended for space exploration, mining and automotive applications with a range of temperature variation in excess of 250°C. A continuous time (CT) sigma delta modulator employing a cascade of integrators with feed forward (CIFF) architecture in a single feedback loop topology is used for implementing the ADC. In order to enable operation in the intended application environments, an RC time constant tuning engine is proposed. The tuning engine is used to maintain linearity of a 10 ksps 20 bit continuous time sigma delta ADC designed for spectroscopy applications in space. The proposed circuit which is based on master slave architecture automatically selects on chip resistors to control RC time constants to an accuracy range of ±5% to ±1%. The tuning range, tuning accuracy and circuit non-idealities are analyzed theoretically. To verify the concept, an experimental chip was fabricated in JAZZ .18µm 1.8V CMOS technology. The tuning engine which occupies an area of .065mm2; consists of only an integrator, a comparator and a shift register. It can achieve a signal to noise and distortion ratio (SNDR) greater than 120dB over a ±40% tuning range.
ContributorsAnabtawi, Nijad (Author) / Barnaby, Hugh (Thesis advisor) / Vermeire, Bert (Committee member) / Gildenblat, Gennady (Committee member) / Chae, Junseok (Committee member) / Arizona State University (Publisher)
Created2011
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Description
The thesis focuses on cost-efficient integration of the electro-chemical residue sensor (ECRS), a novel sensor developed for the in situ and real-time measurement of the residual impurities left on the wafer surface and in the fine structures of patterned wafers during typical rinse processes, and wireless transponder circuitry that is

The thesis focuses on cost-efficient integration of the electro-chemical residue sensor (ECRS), a novel sensor developed for the in situ and real-time measurement of the residual impurities left on the wafer surface and in the fine structures of patterned wafers during typical rinse processes, and wireless transponder circuitry that is based on RFID technology. The proposed technology uses only the NMOS FD-SOI transistors with amorphous silicon as active material with silicon nitride as a gate dielectric. The proposed transistor was simulated under the SILVACO ATLAS Simulation Framework. A parametric study was performed to study the impact of different gate lengths (6 μm to 56 μm), electron motilities (0.1 cm2/Vs to 1 cm2/Vs), gate dielectric (SiO2 and SiNx) and active materials (a-Si and poly-Si) specifications. Level-1 models, that are accurate enough to acquire insight into the circuit behavior and perform preliminary design, were successfully constructed by analyzing drain current and gate to node capacitance characteristics against drain to source and gate to source voltages. Using the model corresponding to SiNx as gate dielectric, a-Si:H as active material with electron mobility equal to 0.4 cm2/V-sec, an operational amplifier was designed and was tested in unity gain configuration at modest load-frequency specifications.
ContributorsPandit, Vedhas (Author) / Vermeire, Bert (Thesis advisor) / Barnaby, Hugh (Committee member) / Chae, Junseok (Committee member) / Arizona State University (Publisher)
Created2010
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Description
The RADiation sensitive Field Effect Transistor (RADFET) has been conventionally used to measure radiation dose levels. These dose sensors are calibrated in such a way that a shift in threshold voltage, due to a build-up of oxide-trapped charge, can be used to estimate the radiation dose. In order to estimate

The RADiation sensitive Field Effect Transistor (RADFET) has been conventionally used to measure radiation dose levels. These dose sensors are calibrated in such a way that a shift in threshold voltage, due to a build-up of oxide-trapped charge, can be used to estimate the radiation dose. In order to estimate the radiation dose level using RADFET, a wired readout circuit is necessary. Using the same principle of oxide-trapped charge build-up, but by monitoring the change in capacitance instead of threshold voltage, a wireless dose sensor can be developed. This RADiation sensitive CAPacitor (RADCAP) mounted on a resonant patch antenna can then become a wireless dose sensor. From the resonant frequency, the capacitance can be extracted which can be mapped back to estimate the radiation dose level. The capacitor acts as both radiation dose sensor and resonator element in the passive antenna loop. Since the MOS capacitor is used in passive state, characterizing various parameters that affect the radiation sensitivity is essential. Oxide processing technique, choice of insulator material, and thickness of the insulator, critically affect the dose response of the sensor. A thicker oxide improves the radiation sensitivity but reduces the dynamic range of dose levels for which the sensor can be used. The oxide processing scheme primarily determines the interface trap charge and oxide-trapped charge development; controlling this parameter is critical to building a better dose sensor.
ContributorsSrinivasan Gopalan, Madusudanan (Author) / Barnaby, Hugh (Thesis advisor) / Holbert, Keith E. (Committee member) / Yu, Hongyu (Committee member) / Arizona State University (Publisher)
Created2010