Matching Items (26)
Description
Advances in software and applications continue to demand advances in memory. The ideal memory would be non-volatile and have maximal capacity, speed, retention time, endurance, and radiation hardness while also having minimal physical size, energy usage, and cost. The programmable metallization cell (PMC) is an emerging memory technology that is likely to surpass flash memory in all the listed ideal memory characteristics. A comprehensive physics-based model is needed to fully understand PMC operation and aid in design optimization. With the intent of advancing the PMC modeling effort, this thesis presents two simulation models for the PMC. The first model is a finite element model based on Silvaco Atlas finite element analysis software. Limitations of the software are identified that make this model inconsistent with the operating mechanism of the PMC. The second model is a physics-based numerical model developed for the PMC. This model is successful in matching data measured from a chalcogenide glass PMC designed and manufactured at ASU. Matched operating characteristics observable in the current and resistance vs. voltage data include the OFF/ON resistances and write/erase and electrodeposition voltage thresholds. Multilevel programming is also explained and demonstrated with the numerical model. The numerical model has already proven useful by revealing some information presented about the operation and characteristics of the PMC.
ContributorsOleksy, David Ryan (Author) / Barnaby, Hugh J (Thesis advisor) / Kozicki, Michael N (Committee member) / Edwards, Arthur H (Committee member) / Arizona State University (Publisher)
Created2013
Description
Low Power, High Speed Analog to Digital Converters continues to remain one of the major building blocks for modern communication systems. Due to continuing trend of the aggressive scaling of the MOS devices, the susceptibility of most of the deep-sub micron CMOS technologies to the ionizing radiation has decreased over the period of time. When electronic circuits fabricated in these CMOS technologies are exposed to ionizing radiations, considerable change in the performance of circuits can be seen over a period of time. The change in the performance can be quantified in terms of decreasing linearity of the circuit which directly relates to the resolution of the circuit. Analog to Digital Converter is one of the most critical blocks of any electronic circuitry sent to space. The degradation in the performance of an Analog to Digital Converter due to radiation effects can jeopardize many research programs related to space. These radiation effects can completely hamper the working of a circuit. This thesis discusses the effects of Ionizing radiation on an 11 bit 325 MSPS pipeline ADC. The ADC is exposed to different doses of radiation and performance is compared.
ContributorsVashisth, Siddharth (Author) / Barnaby, Hugh J (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Mikkola, Esko (Committee member) / Arizona State University (Publisher)
Created2013
Description
Chalcogenide glass (ChG) materials have gained wide attention because of their applications in conductive bridge random access memory (CBRAM), phase change memories (PC-RAM), optical rewritable disks (CD-RW and DVD-RW), microelectromechanical systems (MEMS), microfluidics, and optical communications. One of the significant properties of ChG materials is the change in the resistivity of the material when a metal such as Ag or Cu is added to it by diffusion. This study demonstrates the potential radiation-sensing capabilities of two metal/chalcogenide glass device configurations. Lateral and vertical device configurations sense the radiation-induced migration of Ag+ ions in germanium selenide glasses via changes in electrical resistance between electrodes on the ChG. Before irradiation, these devices exhibit a high-resistance `OFF-state' (in the order of 10E12) but following irradiation, with either 60-Co gamma-rays or UV light, their resistance drops to a low-resistance `ON-state' (around 10E3). Lateral devices have exhibited cyclical recovery with room temperature annealing of the Ag doped ChG, which suggests potential uses in reusable radiation sensor applications. The feasibility of producing inexpensive flexible radiation sensors has been demonstrated by studying the effects of mechanical strain and temperature stress on sensors formed on flexible polymer substrate. The mechanisms of radiation-induced Ag/Ag+ transport and reactions in ChG have been modeled using a finite element device simulator, ATLAS. The essential reactions captured by the simulator are radiation-induced carrier generation, combined with reduction/oxidation for Ag species in the chalcogenide film. Metal-doped ChGs are solid electrolytes that have both ionic and electronic conductivity. The ChG based Programmable Metallization Cell (PMC) is a technology platform that offers electric field dependent resistance switching mechanisms by formation and dissolution of nano sized conductive filaments in a ChG solid electrolyte between oxidizable and inert electrodes. This study identifies silver anode agglomeration in PMC devices following large radiation dose exposure and considers device failure mechanisms via electrical and material characterization. The results demonstrate that by changing device structural parameters, silver agglomeration in PMC devices can be suppressed and reliable resistance switching may be maintained for extremely high doses ranging from 4 Mrad(GeSe) to more than 10 Mrad (ChG).
ContributorsDandamudi, Pradeep (Author) / Kozicki, Michael N (Thesis advisor) / Barnaby, Hugh J (Committee member) / Holbert, Keith E. (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Microprocessors are the processing heart of any digital system and are central to all the technological advancements of the age including space exploration and monitoring. The demands of space exploration require a special class of microprocessors called radiation hardened microprocessors which are less susceptible to radiation present outside the earth's atmosphere, in other words their functioning is not disrupted even in presence of disruptive radiation. The presence of these particles forces the designers to come up with design techniques at circuit and chip levels to alleviate the errors which can be encountered in the functioning of microprocessors. Microprocessor evolution has been very rapid in terms of performance but the same cannot be said about its rad-hard counterpart. With the total data processing capability overall increasing rapidly, the clear lack of performance of the processors manifests as a bottleneck in any processing system. To design high performance rad-hard microprocessors designers have to overcome difficult design problems at various design stages i.e. Architecture, Synthesis, Floorplanning, Optimization, routing and analysis all the while maintaining circuit radiation hardness. The reference design `HERMES' is targeted at 90nm IBM G process and is expected to reach 500Mhz which is twice as fast any processor currently available. Chapter 1 talks about the mechanisms of radiation effects which cause upsets and degradation to the functioning of digital circuits. Chapter 2 gives a brief description of the components which are used in the design and are part of the consistent efforts at ASUVLSI lab culminating in this chip level implementation of the design. Chapter 3 explains the basic digital design ASIC flow and the changes made to it leading to a rad-hard specific ASIC flow used in implementing this chip. Chapter 4 talks about the triple mode redundant (TMR) specific flow which is used in the block implementation, delineating the challenges faced and the solutions proposed to make the flow work. Chapter 5 explains the challenges faced and solutions arrived at while using the top-level flow described in chapter 3. Chapter 6 puts together the results and analyzes the design in terms of basic integrated circuit design constraints.
ContributorsRamamurthy, Chandarasekaran (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh J (Committee member) / Mayhew, David (Committee member) / Arizona State University (Publisher)
Created2013
Description
Semiconductor devices are generally analyzed with relatively simple equations or with detailed computer simulations. Most text-books use these simple equations and show device diagrams that are frequently very simplified and occasionally incorrect. For example, the carrier densities near the pinch-off point in MOSFETs and JFETs and the minority carrier density in the base near the reverse-biased base-collector junction are frequently assumed to be zero or near zero. Also the channel thickness at the pinch-off point is often shown to approach zero. None of these assumptions can be correct. The research in thesis addresses these points. I simulated the carrier densities, potentials, electric fields etc. of MOSFETs, BJTs and JFETs at and near the pinch-off regions to determine exactly what happens there. I also simulated the behavior of the quasi-Fermi levels. For MOSFETs, the channel thickness expands slightly before the pinch-off point and then spreads out quickly in a triangular shape and the space-charge region under the channel actually shrinks as the potential increases from source to drain. For BJTs, with collector-base junction reverse biased, most minority carriers diffuse through the base from emitter to collector very fast, but the minority carrier concentration at the collector-base space-charge region is not zero. For JFETs, the boundaries of the space-charge region are difficult to determine, the channel does not disappear after pinch off, the shape of channel is always tapered, and the carrier concentration in the channel decreases progressively. After simulating traditional sized devices, I also simulated typical nano-scaled devices and show that they behave similarly to large devices. These simulation results provide a more complete understanding of device physics and device operation in those regions usually not addressed in semiconductor device physics books.
ContributorsYang, Xuan (Author) / Schroder, Dieter K. (Thesis advisor) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2011
Description
Radiation-induced gain degradation in bipolar devices is considered to be the primary threat to linear bipolar circuits operating in the space environment. The damage is primarily caused by charged particles trapped in the Earth's magnetosphere, the solar wind, and cosmic rays. This constant radiation exposure leads to early end-of-life expectancies for many electronic parts. Exposure to ionizing radiation increases the density of oxide and interfacial defects in bipolar oxides leading to an increase in base current in bipolar junction transistors. Radiation-induced excess base current is the primary cause of current gain degradation. Analysis of base current response can enable the measurement of defects generated by radiation exposure. In addition to radiation, the space environment is also characterized by extreme temperature fluctuations. Temperature, like radiation, also has a very strong impact on base current. Thus, a technique for separating the effects of radiation from thermal effects is necessary in order to accurately measure radiation-induced damage in space. This thesis focuses on the extraction of radiation damage in lateral PNP bipolar junction transistors and the space environment. It also describes the measurement techniques used and provides a quantitative analysis methodology for separating radiation and thermal effects on the bipolar base current.
ContributorsCampola, Michael J (Author) / Barnaby, Hugh J (Thesis advisor) / Holbert, Keith E. (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2011
Description
Programmable metallization cell (PMC) technology is based on an electrochemical phenomenon in which a metallic electrodeposit can be grown or dissolved between two electrodes depending on the voltage applied between them. Devices based on this phenomenon exhibit a unique, self-healing property, as a broken metallic structure can be healed by applying an appropriate voltage between the two broken ends. This work explores methods of fabricating interconnects and switches based on PMC technology on flexible substrates. The objective was the evaluation of the feasibility of using this technology in flexible electronics applications in which reliability is a primary concern. The re-healable property of the interconnect is characterized for the silver doped germanium selenide (Ag-Ge-Se) solid electrolyte system. This property was evaluated by measuring the resistances of the healed interconnect structures and comparing these to the resistances of the unbroken structures. The reliability of the interconnects in both unbroken and healed states is studied by investigating the resistances of the structures to DC voltages, AC voltages and different temperatures as a function of time. This work also explores replacing silver with copper for these interconnects to enhance their reliability. A model for PMC-based switches on flexible substrates is proposed and compared to the observed device behavior with the objective of developing a formal design methodology for these devices. The switches were subjected to voltage sweeps and their resistance was investigated as a function of sweep voltage. The resistance of the switches as a function of voltage pulse magnitude when placed in series with a resistance was also investigated. A model was then developed to explain the behavior of these devices. All observations were based on statistical measurements to account for random errors. The results of this work demonstrate that solid electrolyte based interconnects display self-healing capability, which depends on the applied healing voltage and the current limit. However, they fail at lower current densities than metal interconnects due to an ion-drift induced failure mechanism. The results on the PMC based switches demonstrate that a model comprising a Schottky diode in parallel with a variable resistor predicts the behavior of the device.
ContributorsBaliga, Sunil Ravindranath (Author) / Kozicki, Michael N (Thesis advisor) / Schroder, Dieter K. (Committee member) / Chae, Junseok (Committee member) / Alford, Terry L. (Committee member) / Arizona State University (Publisher)
Created2011
Description
The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.
ContributorsSanchez Esqueda, Ivan (Author) / Barnaby, Hugh J (Committee member) / Schroder, Dieter (Thesis advisor) / Schroder, Dieter K. (Committee member) / Holbert, Keith E. (Committee member) / Gildenblat, Gennady (Committee member) / Arizona State University (Publisher)
Created2011
Description
This thesis discusses the evolution of conduction mechanism in the silver (Ag) on zinc oxide (ZnO) thin film system with respect to the Ag morphology. As a plausible substitute for indium tin oxide (ITO), TCO/Metal/TCO (TMT) structure has received a lot of attentions as a prospective ITO substitute due to its low resistivity and desirable transmittance. However, the detailed conduction mechanism is not fully understood. In an attempt to investigate the conduction mechanism of the ZnO/Ag/ZnO thin film system with respect to the Ag microstructure, the top ZnO layer is removed, which offers a better view of Ag morphology by using scanning electron microscopy (SEM). With 2 nm thick Ag layer, it is seen that the Ag forms discrete islands with small islands size (r), but large separation (s); also the effective resistivity of the system is extremely high. This regime is designated as dielectric zone. In this regime, thermionic emission and activated tunneling conduction mechanisms are considered. Based on simulations, when "s" was beyond 6 nm, thermionic emission dominates; with "s" less than 6 nm, activated tunneling is the dominating mechanism. As the Ag thickness increases, the individual islands coalesce and Ag clusters are formed. At certain Ag thickness, there are one or several Ag clusters that percolate the ZnO film, and the effective resistivity of the system exhibits a tremendous drop simultaneously, because the conducting electrons do not need to overcome huge ZnO barrier to transport. This is recognized as percolation zone. As the Ag thickness grows, Ag film becomes more continuous and there are no individual islands left on the surface. The effective resistivity decreases and is comparable to the characteristics of metallic materials, so this regime is categorized as metallic zone. The simulation of the Ag thin film resistivity is performed in terms of Ag thickness, and the experimental data fits the simulation well, which supports the proposed models. Hall measurement and four point probe measurement are carried out to characterize the electrical properties of the thin film system.
ContributorsZhang, Shengke (Author) / Alford, Terry L. (Thesis advisor) / Schroder, Dieter K. (Committee member) / Tasooji, Amaneh (Committee member) / Arizona State University (Publisher)
Created2012
Description
High-Resistivity Silicon (HRS) substrates are important for low-loss, high-performance microwave and millimeter wave devices in high-frequency telecommunication systems. The highest resistivity of up to ~10,000 ohm.cm is Float Zone (FZ) grown Si which is produced in small quantities and moderate wafer diameter. The more common Czochralski (CZ) Si can achieve resistivities of around 1000 ohm.cm, but the wafers contain oxygen that can lead to thermal donor formation with donor concentration significantly higher (~1015 cm-3) than the dopant concentration (~1012-1013 cm-3) of such high-resistivity Si leading to resistivity changes and possible type conversion of high-resistivity p-type silicon. In this research capacitance-voltage (C-V) characterization is employed to study the donor formation and type conversion of p-type High-resistivity Silicon-On-Insulator (HRSOI) wafers and the challenges involved in C-V characterization of HRSOI wafers using a Schottky contact are highlighted. The maximum capacitance of bulk or Silicon-On-Insulator (SOI) wafers is governed by the gate/contact area. During C-V characterization of high-resistivity SOI wafers with aluminum contacts directly on the Si film (Schottky contact); it was observed that the maximum capacitance is much higher than that due to the contact area, suggesting bias spreading due to the distributed transmission line of the film resistance and the buried oxide capacitance. In addition, an "S"-shape C-V plot was observed in the accumulation region. The effects of various factors, such as: frequency, contact and substrate sizes, gate oxide, SOI film thickness, film and substrate doping, carrier lifetime, contact work-function, temperature, light, annealing temperature and radiation on the C-V characteristics of HRSOI wafers are studied. HRSOI wafers have the best crosstalk prevention capability compared to other types of wafers, which plays a major role in system-on-chip configuration to prevent coupling between high frequency digital and sensitive analog circuits. Substrate crosstalk in HRSOI and various factors affecting the crosstalk, such as: substrate resistivity, separation between devices, buried oxide (BOX) thickness, radiation, temperature, annealing, light, and device types are discussed. Also various ways to minimize substrate crosstalk are studied and a new characterization method is proposed. Owing to their very low doping concentrations and the presence of oxygen in CZ wafers, HRS wafers pose a challenge in resistivity measurement using conventional techniques such as four-point probe and Hall measurement methods. In this research the challenges in accurate resistivity measurement using four-point probe, Hall method, and C-V profile are highlighted and a novel approach to extract resistivity of HRS wafers based on Impedance Spectroscopy measurements using polymer dielectrics such as Polystyrene and Poly Methyl Methacrylate (PMMA) is proposed.
ContributorsNayak, Pinakpani (Author) / Schroder, Dieter K. (Thesis advisor) / Vasileska, Dragica (Committee member) / Kozicki, Michael (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2012