Matching Items (14)
Description
Digital systems are increasingly pervading in the everyday lives of humans. The security of these systems is a concern due to the sensitive data stored in them. The physically unclonable function (PUF) implemented on hardware provides a way to protect these systems. Static random-access memories (SRAMs) are designed and used as a strong PUF to generate random numbers unique to the manufactured integrated circuit (IC).
Digital systems are important to the technological improvements in space exploration. Space exploration requires radiation hardened microprocessors which minimize the functional disruptions in the presence of radiation. The design highly efficient radiation-hardened microprocessor for enabling spacecraft (HERMES) is a radiation-hardened microprocessor with performance comparable to the commercially available designs. These designs are manufactured using a foundry complementary metal-oxide semiconductor (CMOS) 55-nm triple-well process. This thesis presents the post silicon validation results of the HERMES and the PUF mode of SRAM across process corners.
Chapter 1 gives an overview of the blocks implemented on the test chip 25. It also talks about the pre-silicon functional verification methodology used for the test chip. Chapter 2 discusses about the post silicon testing setup of test chip 25 and the validation of the setup. Chapter 3 describes the architecture and the test bench of the HERMES along with its testing results. Chapter 4 discusses the test bench and the perl scripts used to test the SRAM along with its testing results. Chapter 5 gives a summary of the post-silicon validation results of the HERMES and the PUF mode of SRAM.
Digital systems are important to the technological improvements in space exploration. Space exploration requires radiation hardened microprocessors which minimize the functional disruptions in the presence of radiation. The design highly efficient radiation-hardened microprocessor for enabling spacecraft (HERMES) is a radiation-hardened microprocessor with performance comparable to the commercially available designs. These designs are manufactured using a foundry complementary metal-oxide semiconductor (CMOS) 55-nm triple-well process. This thesis presents the post silicon validation results of the HERMES and the PUF mode of SRAM across process corners.
Chapter 1 gives an overview of the blocks implemented on the test chip 25. It also talks about the pre-silicon functional verification methodology used for the test chip. Chapter 2 discusses about the post silicon testing setup of test chip 25 and the validation of the setup. Chapter 3 describes the architecture and the test bench of the HERMES along with its testing results. Chapter 4 discusses the test bench and the perl scripts used to test the SRAM along with its testing results. Chapter 5 gives a summary of the post-silicon validation results of the HERMES and the PUF mode of SRAM.
ContributorsMedapuram, Sai Bharadwaj (Author) / Clark, Lawrence T (Thesis advisor) / Allee, David R. (Committee member) / Brunhaver, John S (Committee member) / Arizona State University (Publisher)
Created2017
Description
Electric field imaging allows for a low cost, compact, non-invasive, non-ionizing alternative to other methods of imaging. It has many promising industrial applications including security, safely imaging power lines at construction sites, finding sources of electromagnetic interference, geo-prospecting, and medical imaging. The work presented in this dissertation concerns low frequency electric field imaging: the physics, hardware, and various methods of achieving it.
Electric fields have historically been notoriously difficult to work with due to how intrinsically noisy the data is in electric field sensors. As a first contribution, an in-depth study demonstrates just how prevalent electric field noise is. In field tests, various cables were placed underneath power lines. Despite being shielded, the 60 Hz power line signal readily penetrated several types of cables.
The challenges of high noise levels were largely addressed by connecting the output of an electric field sensor to a lock-in amplifier. Using the more accurate means of collecting electric field data, D-dot sensors were arrayed in a compact grid to resolve electric field images as a second contribution. This imager has successfully captured electric field images of live concealed wires and electromagnetic interference.
An active method was developed as a third contribution. In this method, distortions created by objects when placed in a known electric field are read. This expands the domain of what can be imaged because the object does not need to be a time-varying electric field source. Images of dielectrics (e.g. bodies of water) and DC wires were captured using this new method.
The final contribution uses a collection of one-dimensional electric field images, i.e. projections, to reconstruct a two-dimensional image. This was achieved using algorithms based in computed tomography such as filtered backprojection. An algebraic approach was also used to enforce sparsity regularization with the L1 norm, further improving the quality of some images.
Electric fields have historically been notoriously difficult to work with due to how intrinsically noisy the data is in electric field sensors. As a first contribution, an in-depth study demonstrates just how prevalent electric field noise is. In field tests, various cables were placed underneath power lines. Despite being shielded, the 60 Hz power line signal readily penetrated several types of cables.
The challenges of high noise levels were largely addressed by connecting the output of an electric field sensor to a lock-in amplifier. Using the more accurate means of collecting electric field data, D-dot sensors were arrayed in a compact grid to resolve electric field images as a second contribution. This imager has successfully captured electric field images of live concealed wires and electromagnetic interference.
An active method was developed as a third contribution. In this method, distortions created by objects when placed in a known electric field are read. This expands the domain of what can be imaged because the object does not need to be a time-varying electric field source. Images of dielectrics (e.g. bodies of water) and DC wires were captured using this new method.
The final contribution uses a collection of one-dimensional electric field images, i.e. projections, to reconstruct a two-dimensional image. This was achieved using algorithms based in computed tomography such as filtered backprojection. An algebraic approach was also used to enforce sparsity regularization with the L1 norm, further improving the quality of some images.
ContributorsChung, Hugh Emanuel (Author) / Allee, David R. (Thesis advisor) / Cochran, Douglas (Committee member) / Aberle, James T (Committee member) / Phillips, Stephen M (Committee member) / Arizona State University (Publisher)
Created2017
Description
Modern-day integrated circuits are very capable, often containing more than a billion transistors. For example, the Intel Ivy Bridge 4C chip has about 1.2 billion transistors on a 160 mm2 die. Designing such complex circuits requires automation. Therefore, these designs are made with the help of computer aided design (CAD) tools. A major part of this custom design flow for application specific integrated circuits (ASIC) is the design of standard cell libraries. Standard cell libraries are a collection of primitives from which the automatic place and route (APR) tools can choose a collection of cells and implement the design that is being put together. To operate efficiently, the CAD tools require multiple views of each cell in the standard cell library. This data is obtained by characterizing the standard cell libraries and compiling the results in formats that the tools can easily understand and utilize.
My thesis focusses on the design and characterization of one such standard cell library in the ASAP7 7 nm predictive design kit (PDK). The complete design flow, starting from the choice of the cell architecture, design of the cell layouts and the various decisions made in that process to obtain optimum results, to the characterization of those cells using the Liberate tool provided by Cadence design systems Inc., is discussed in this thesis. The end results of the characterized library are used in the APR of a few open source register-transfer logic (RTL) projects and the efficiency of the library is demonstrated.
My thesis focusses on the design and characterization of one such standard cell library in the ASAP7 7 nm predictive design kit (PDK). The complete design flow, starting from the choice of the cell architecture, design of the cell layouts and the various decisions made in that process to obtain optimum results, to the characterization of those cells using the Liberate tool provided by Cadence design systems Inc., is discussed in this thesis. The end results of the characterized library are used in the APR of a few open source register-transfer logic (RTL) projects and the efficiency of the library is demonstrated.
ContributorsVangala, Manoj (Author) / Clark, Lawrence T (Thesis advisor) / Brunhaver, John S (Committee member) / Allee, David R. (Committee member) / Arizona State University (Publisher)
Created2017
Description
Recent years have seen fin field effect transistors (finFETs) dominate modern complementary metal oxide semiconductor (CMOS) processes, [1][2], e.g., at the sub 20 nm technology nodes, as they alleviate short channel effects, provide lower leakage, and enable some continued VDD scaling. However, a realistic finFET based predictive process design kit (PDK) that supports investigation into both circuit and physical design, encompassing all aspects of digital design, for academic use has been unavailable. While the finFET based FreePDK15 was supplemented with a standard cell library, it lacked full physical verification (LVS) and parasitic extraction at the time [3][4]. Consequently, the only available sub 45 nm educational PDKs are the planar CMOS based Synopsys 32/28 nm and FreePDK45 (45 nm PDK) [5][6]. The cell libraries available for those processes are not realistic since they use large cell heights, in contrast to recent industry trends. Additionally, the SRAM rules and cells provided by these PDKs are not realistic. Because finFETs have a 3D structure, which affects transistor density, using planar libraries scaled to sub 22 nm dimensions for research is likely to give poor accuracy.
Commercial libraries and PDKs, especially for advanced nodes, are often difficult to obtain for academic use, and access to the actual physical layouts is even more restricted. Furthermore, the necessary non disclosure agreements (NDAs) are un manageable for large university classes and the plethora of design rules can distract from the key points. NDAs also make it difficult for the publication of physical design as these may disclose proprietary design rules and structures.
This work focuses on the development of realistic PDKs for academic use that overcome these limitations. These PDKs, developed for the N7 and N5 nodes, even before 7 nm and 5 nm processes were available in industry, are thus predictive. The predictions have been based on publications of the continually improving lithography, as well as estimates of what would be available at N7 and N5. For the most part, these assumptions have been accurate with regards to N7, except for the expectation that extreme ultraviolet (EUV) lithography would be widely available, which has turned out to be optimistic.
Commercial libraries and PDKs, especially for advanced nodes, are often difficult to obtain for academic use, and access to the actual physical layouts is even more restricted. Furthermore, the necessary non disclosure agreements (NDAs) are un manageable for large university classes and the plethora of design rules can distract from the key points. NDAs also make it difficult for the publication of physical design as these may disclose proprietary design rules and structures.
This work focuses on the development of realistic PDKs for academic use that overcome these limitations. These PDKs, developed for the N7 and N5 nodes, even before 7 nm and 5 nm processes were available in industry, are thus predictive. The predictions have been based on publications of the continually improving lithography, as well as estimates of what would be available at N7 and N5. For the most part, these assumptions have been accurate with regards to N7, except for the expectation that extreme ultraviolet (EUV) lithography would be widely available, which has turned out to be optimistic.
ContributorsVashishtha, Vinay (Author) / Clark, Lawrence T. (Thesis advisor) / Allee, David R. (Committee member) / Ogras, Umit Y. (Committee member) / Seo, Jae sun (Committee member) / Arizona State University (Publisher)
Created2019