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ContributorsLovelady, Alexis (Performer) / ASU Library. Music Library (Publisher)
Created2018-04-08
Description
This study treats in some depth a contemporary solo piano work, "Arirang Variations" (2006) by Edward "Teddy" Niedermaier (b. 1983). Though Niedermaier is an American composer and pianist, he derives his inspiration for that work from four types of Korean arirang: "Arirang," "Raengsanmopan Older Babe Arirang," "Gangwondo Arirang" and "Kin Arirang." The analysis of "Arirang Variations" focuses primarily on how the composer adapts arirang in each variation and develops them into his own musical language. A salient feature of Niedermaier's composition is his combination of certain contradictions: traditional and contemporary styles, and Western and Eastern musical styles. In order to discuss in detail the musical elements of arirang used in "Arirang Variations," scores of all the arirang Niedermaier references are included with the discussion of each. Unfortunately, sources concerning three of these were limited to a single book by Yon-gap Kim, Pukhan Arirang Yongu (A Study of North Korean Arirang), because "Raengsanmopan Older Babe Arirang," "Gangwondo Arirang" and "Kin Arirang"are North Korean versions of arirang. Since arirang are the most important Korean folk song genre, basic information concerning such features of Korean traditional musical elements as scales, vocal techniques, rhythms and types of folk songs are provided along with an overview of the history and origins of arirang. Given that each arirang has distinctive characteristics that vary by region, the four best-known types of arirang are introduced to demonstrate these differences.
ContributorsPark, Hyunjin (Author) / Meir, Baruch (Thesis advisor) / Campbell, Andrew (Committee member) / Levy, Benjamin (Committee member) / Thompson, Janice (Committee member) / Arizona State University (Publisher)
Created2011
ContributorsDruesedow, Elizabeth (Performer) / ASU Library. Music Library (Publisher)
Created2018-04-07
Description
Thanks to continuous technology scaling, intelligent, fast and smaller digital systems are now available at affordable costs. As a result, digital systems have found use in a wide range of application areas that were not even imagined before, including medical (e.g., MRI, remote or post-operative monitoring devices, etc.), automotive (e.g., adaptive cruise control, anti-lock brakes, etc.), security systems (e.g., residential security gateways, surveillance devices, etc.), and in- and out-of-body sensing (e.g., capsule swallowed by patients measuring digestive system pH, heart monitors, etc.). Such computing systems, which are completely embedded within the application, are called embedded systems, as opposed to general purpose computing systems. In the design of such embedded systems, power consumption and reliability are indispensable system requirements. In battery operated portable devices, the battery is the single largest factor contributing to device cost, weight, recharging time, frequency and ultimately its usability. For example, in the Apple iPhone 4 smart-phone, the battery is $40\%$ of the device weight, occupies $36\%$ of its volume and allows only $7$ hours (over 3G) of talk time. As embedded systems find use in a range of sensitive applications, from bio-medical applications to safety and security systems, the reliability of the computations performed becomes a crucial factor. At our current technology-node, portable embedded systems are prone to expect failures due to soft errors at the rate of once-per-year; but with aggressive technology scaling, the rate is predicted to increase exponentially to once-per-hour. Over the years, researchers have been successful in developing techniques, implemented at different layers of the design-spectrum, to improve system power efficiency and reliability. Among the layers of design abstraction, I observe that the interface between the compiler and processor micro-architecture possesses a unique potential for efficient design optimizations. A compiler designer is able to observe and analyze the application software at a finer granularity; while the processor architect analyzes the system output (power, performance, etc.) for each executed instruction. At the compiler micro-architecture interface, if the system knowledge at the two design layers can be integrated, design optimizations at the two layers can be modified to efficiently utilize available resources and thereby achieve appreciable system-level benefits. To this effect, the thesis statement is that, ``by merging system design information at the compiler and micro-architecture design layers, smart compilers can be developed, that achieve reliable and power-efficient embedded computing through: i) Pure compiler techniques, ii) Hybrid compiler micro-architecture techniques, and iii) Compiler-aware architectures''. In this dissertation demonstrates, through contributions in each of the three compiler-based techniques, the effectiveness of smart compilers in achieving power-efficiency and reliability in embedded systems.
ContributorsJeyapaul, Reiley (Author) / Shrivastava, Aviral (Thesis advisor) / Vrudhula, Sarma (Committee member) / Clark, Lawrence (Committee member) / Colbourn, Charles (Committee member) / Arizona State University (Publisher)
Created2012
ContributorsShi, Zhan (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-26
ContributorsQualls, Aliyah (Performer) / Winseck, Kevin (Performer) / Solari, John (Performer) / ASU Library. Music Library (Publisher)
Created2018-04-03
Description
Negative bias temperature instability (NBTI) is a leading aging mechanism in modern digital and analog circuits. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction under statistical variations and Dynamic Voltage Scaling (DVS) in real circuit operation. To overcome these barriers, the modeling effort in this work (1) practically explains the aging statistics due to randomness in number of traps with log(t) model, accurately predicting the mean and variance shift; (2) proposes cycle-to-cycle model (from the first-principle of trapping) to handle aging under multiple supply voltages, predicting the non-monotonic behavior under DVS (3) presents a long-term model to estimate a tight upper bound of dynamic aging over multiple cycles, and (4) comprehensively validates the new set of aging models with 65nm statistical silicon data. Compared to previous models, the new set of aging models capture the aging variability and the essential role of the recovery phase under DVS, reducing unnecessary guard-banding during the design stage. With CMOS technology scaling, design for reliability has become an important step in the design cycle, and increased the need for efficient and accurate aging simulation methods during the design stage. NBTI induced delay shifts in logic paths are asymmetric in nature, as opposed to averaging effect due to recovery assumed in traditional aging analysis. Timing violations due to aging, in particular, are very sensitive to the standby operation regime of a digital circuit. In this report, by identifying the critical moments in circuit operation and considering the asymmetric aging effects, timing violations under NBTI effect are correctly predicted. The unique contributions of the simulation flow include: (1) accurate modeling of aging induced delay shift due to threshold voltage (Vth) shift using only the delay dependence on supply voltage from cell library; (2) simulation flow for asymmetric aging analysis is proposed and conducted at critical points in circuit operation; (3) setup and hold timing violations due to NBTI aging in logic and clock buffer are investigated in sequential circuits and (4) proposed framework is tested in VLSI applications such DDR memory circuits. This methodology is comprehensively demonstrated with ISCAS89 benchmark circuits using a 45nm Nangate standard cell library characterized using predictive technology models. Our proposed design margin assessment provides design insights and enables resilient techniques for mitigating digital circuit aging.
ContributorsVelamala, Jyothi Bhaskarr (Author) / Cao, Yu (Thesis advisor) / Clark, Lawrence (Committee member) / Chakrabarti, Chaitali (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
ContributorsYu, Xuehui (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-31
ContributorsMcClain, Katelyn (Performer) / Buringrud, Deanna (Contributor) / Lee, Juhyun (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-31
ContributorsCummiskey, Hannah (Performer) / Kim, Olga (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-23