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Description
This document is intended to show the various kinds of stylistically appropriate melodic and rhythmic ornamentation that can be used in the improvisation of the Sarabandes by J.S. Bach. Traditional editions of Bach's and other Baroque-era keyboard works have reflected evolving historical trends. The historical performance movement and other attempts to "clean up" pre-1950s romanticized performances have greatly limited the freedom and experimentation that was the original intention of these dances. Prior to this study, few ornamented editions of these works have been published. Although traditional practices do not necessarily encourage classical improvisation in performance I argue that manipulation of the melodic and rhythmic layers over the established harmonic progressions will not only provide diversity within the individual dance movements, but also further engage the ears of the performer and listener which encourages further creative exploration. I will focus this study on the ornamentation of all six Sarabandes from J.S. Bach's French Suites and show how various types of melodic and rhythmic variation can provide aurally pleasing alternatives to the composed score without disrupting the harmonic fluency. The author intends this document to be used as a pedagogical tool and the fully ornamented Sarabandes from J.S. Bach's French Suites are included with this document.
ContributorsOakley, Ashley (Author) / Meir, Baruch (Thesis advisor) / Campbell, Andrew (Committee member) / Norton, Kay (Committee member) / Pagano, Caio (Committee member) / Ryan, Russell (Committee member) / Arizona State University (Publisher)
Created2013
Description
About piano students who display disruptive behavior and perform far below reasonable expectations, teachers first conclude that they are lazy, rude, disinterested, and/or lacking intelligence or ability. Most dismiss such students from studios and advise parents to discontinue lessons. In truth, many of these students are both highly gifted and also have a learning disability. Examined literature shows that the incidence of dyslexia and other learning disabilities in the gifted learner population is several times that of the regular learner population. Although large volumes of research have been devoted to dyslexia, and more recently to dyslexia and music (in the classroom and some in individual instrumental instruction), there is no evidence of the same investigation in relation to the specific needs of highly gifted dyslexic students in learning to play the piano. This project examines characteristics of giftedness and dyslexia, gifted learners with learning disabilities, and the difficulties they encounter in learning to read music and play keyboard instruments. It includes historical summaries of author's experience with such students and description of their progress and success. They reveal some of practical strategies that evolved through several decades of teaching regular and gifted dyslexic students that helped them overcome the challenges and learn to play the piano. Informal conversations and experience exchanges with colleagues, as well as a recently completed pilot study also showed that most piano pedagogues had no formal opportunity to learn about this issue and to be empowered to teach these very special students. The author's hope is to offer personal insights, survey of current knowledge, and practical suggestions that will not only assist piano instructors to successfully teach highly gifted learners with dyslexia, but also inspire them to learn more about the topic.
ContributorsVladikovic, Jelena (Author) / Humphreys, Jere T. (Thesis advisor) / Meir, Baruch (Thesis advisor) / Norton, Kay (Committee member) / Hamilton, Robert (Committee member) / Arizona State University (Publisher)
Created2013
Description
Memories play an integral role in today's advanced ICs. Technology scaling has enabled high density designs at the price paid for impact due to variability and reliability. It is imperative to have accurate methods to measure and extract the variability in the SRAM cell to produce accurate reliability projections for future technologies. This work presents a novel test measurement and extraction technique which is non-invasive to the actual operation of the SRAM memory array. The salient features of this work include i) A single ended SRAM test structure with no disturbance to SRAM operations ii) a convenient test procedure that only requires quasi-static control of external voltages iii) non-iterative method that extracts the VTH variation of each transistor from eight independent switch point measurements. With the present day technology scaling, in addition to the variability with the process, there is also the impact of other aging mechanisms which become dominant. The various aging mechanisms like Negative Bias Temperature Instability (NBTI), Channel Hot Carrier (CHC) and Time Dependent Dielectric Breakdown (TDDB) are critical in the present day nano-scale technology nodes. In this work, we focus on the impact of NBTI due to aging in the SRAM cell and have used Trapping/De-Trapping theory based log(t) model to explain the shift in threshold voltage VTH. The aging section focuses on the following i) Impact of Statistical aging in PMOS device due to NBTI dominates the temporal shift of SRAM cell ii) Besides static variations , shifting in VTH demands increased guard-banding margins in design stage iii) Aging statistics remain constant during the shift, presenting a secondary effect in aging prediction. iv) We have investigated to see if the aging mechanism can be used as a compensation technique to reduce mismatch due to process variations. Finally, the entire test setup has been tested in SPICE and also validated with silicon and the results are presented. The method also facilitates the study of design metrics such as static, read and write noise margins and also the data retention voltage and thus help designers to improve the cell stability of SRAM.
ContributorsRavi, Venkatesa (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Clark, Lawrence (Committee member) / Arizona State University (Publisher)
Created2013
Description
ABSTRACT The D flip flop acts as a sequencing element while designing any pipelined system. Radiation Hardening by Design (RHBD) allows hardened circuits to be fabricated on commercially available CMOS manufacturing process. Recently, single event transients (SET's) have become as important as single event upset (SEU) in radiation hardened high speed digital designs. A novel temporal pulse based RHBD flip-flop design is presented. Temporally delayed pulses produced by a radiation hardened pulse generator design samples the data in three redundant pulse latches. The proposed RHBD flip-flop has been statistically designed and fabricated on 90 nm TSMC LP process. Detailed simulations of the flip-flop operation in both normal and radiation environments are presented. Spatial separation of critical nodes for the physical design of the flip-flop is carried out for mitigating multi-node charge collection upsets. The proposed flip-flop is also used in commercial CAD flows for high performance chip designs. The proposed flip-flop is used in the design and auto-place-route (APR) of an advanced encryption system and the metrics analyzed.
ContributorsKumar, Sushil (Author) / Clark, Lawrence (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2014
Description
This work describes the development of automated flows to generate pad rings, mixed signal power grids, and mega cells in a multi-project test chip. There were three major design flows that were created to create the test chip. The first was the pad ring which was used as the staring block for creating the test chip. This flow put all of the signals for the chip in the order that was wanted along the outside of the die along with creation of the power ring that is used to supply the chip with a robust power source.
The second flow that was created was used to put together a flash block that is based off of a XILIX XCFXXP. This flow was somewhat similar to how the pad ring flow worked except that optimizations and a clock tree was added into the flow. There was a couple of design redoes due to timing and orientation constraints.
Finally, the last flow that was created was the top level flow which is where all of the components are combined together to create a finished test chip ready for fabrication. The main components that were used were the finished flash block, HERMES, test structures, and a clock instance along with the pad ring flow for the creation of the pad ring and power ring.
Also discussed is some work that was done on a previous multi-project test chip. The work that was done was the creation of power gaters that were used like switches to turn the power on and off for some flash modules. To control the power gaters the functionality change of some pad drivers was done so that they output a higher voltage than what is seen in the core of the chip.
The second flow that was created was used to put together a flash block that is based off of a XILIX XCFXXP. This flow was somewhat similar to how the pad ring flow worked except that optimizations and a clock tree was added into the flow. There was a couple of design redoes due to timing and orientation constraints.
Finally, the last flow that was created was the top level flow which is where all of the components are combined together to create a finished test chip ready for fabrication. The main components that were used were the finished flash block, HERMES, test structures, and a clock instance along with the pad ring flow for the creation of the pad ring and power ring.
Also discussed is some work that was done on a previous multi-project test chip. The work that was done was the creation of power gaters that were used like switches to turn the power on and off for some flash modules. To control the power gaters the functionality change of some pad drivers was done so that they output a higher voltage than what is seen in the core of the chip.
ContributorsLieb, Christopher (Author) / Clark, Lawrence (Thesis advisor) / Holbert, Keith E. (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2015
Description
Geirr Tveitt (1908-1981) was a central figure of the national movement in Norwegian cultural life during the 1930s. He studied composition with masters such as Arthur Honegger, Heitor Villa-Lobos, and Nadia Boulanger, achieving international acclaim for many of his works. However, his native Norway was slow to follow this praise, as post-World War II intellectuals disregarded anything that resembled nationalism. Tveitt's music was considered obsolete. He became isolated and withdrawn and died in 1981 after a house fire destroyed the manuscripts of nearly three hundred opuses, leaving only a handful of works, some of which were not yet published. Tveitt was raised in a remote part of Norway where the folk tradition was strong. Because of his close ties with the Hardanger community, he was able to bring to light many undiscovered folk tunes and exceptional practices. Tveitt utilizes this first-hand knowledge in his works for solo piano, and successfully combines them with his roots in both Germanic and Nordic traditions, eventually becoming a well-known and respected composer to the Norwegian people. However, he remains virtually unknown to the rest of the world. All of his music was deeply influenced by folk traditions and instruments. Techniques such as planing, drones, modal scales and passages, ornamentation, and simple melodies are pervasive in each piece, and are often the building blocks of main themes and motives. Because of the ambiguity of the status of many works, this paper examines only his published works for solo piano. Discussions of each piece will focus on folk influences within each work, including basic form, texture, and pianistic concerns.
ContributorsHunter, Karali (Author) / Meir, Baruch (Thesis advisor) / Carpenter, Ellon (Committee member) / Ryan, Russell (Committee member) / Arizona State University (Publisher)
Created2014
Description
The space environment comprises cosmic ray particles, heavy ions and high energy electrons and protons. Microelectronic circuits used in space applications such as satellites and space stations are prone to upsets induced by these particles. With transistor dimensions shrinking due to continued scaling, terrestrial integrated circuits are also increasingly susceptible to radiation upsets. Hence radiation hardening is a requirement for microelectronic circuits used in both space and terrestrial applications.
This work begins by exploring the different radiation hardened flip-flops that have been proposed in the literature and classifies them based on the different hardening techniques.
A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient tolerance is demonstrated by simulations using it in a radiation hardened by design master slave flip-flop (FF). Using the proposed delay element saves up to 25% total FF power at 50% activity factor. The delay element is used in the implementation of an 8-bit, 8051 designed in the TSMC 130 nm bulk CMOS.
A single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate in most modern scaled process technologies. The design of flip-flops is made more difficult with increasing multi-node charge collection, which requires that charge storage and other sensitive nodes be separated so that one impinging radiation particle does not affect redundant nodes simultaneously. We describe a correct-by-construction design methodology to determine a-priori which hardened FF nodes must be separated, as well as a general interleaving scheme to achieve this separation. We apply the methodology to radiation hardened flip-flops and demonstrate optimal circuit physical organization for protection against multi-node charge collection.
Finally, the methodology is utilized to provide critical node separation for a new hardened flip-flop design that reduces the power and area by 31% and 35% respectively compared to a temporal FF with similar hardness. The hardness is verified and compared to other published designs via the proposed systematic simulation approach that comprehends multiple node charge collection and tests resiliency to upsets at all internal and input nodes. Comparison of the hardness, as measured by estimated upset cross-section, is made to other published designs. Additionally, the importance of specific circuit design aspects to achieving hardness is shown.
This work begins by exploring the different radiation hardened flip-flops that have been proposed in the literature and classifies them based on the different hardening techniques.
A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient tolerance is demonstrated by simulations using it in a radiation hardened by design master slave flip-flop (FF). Using the proposed delay element saves up to 25% total FF power at 50% activity factor. The delay element is used in the implementation of an 8-bit, 8051 designed in the TSMC 130 nm bulk CMOS.
A single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate in most modern scaled process technologies. The design of flip-flops is made more difficult with increasing multi-node charge collection, which requires that charge storage and other sensitive nodes be separated so that one impinging radiation particle does not affect redundant nodes simultaneously. We describe a correct-by-construction design methodology to determine a-priori which hardened FF nodes must be separated, as well as a general interleaving scheme to achieve this separation. We apply the methodology to radiation hardened flip-flops and demonstrate optimal circuit physical organization for protection against multi-node charge collection.
Finally, the methodology is utilized to provide critical node separation for a new hardened flip-flop design that reduces the power and area by 31% and 35% respectively compared to a temporal FF with similar hardness. The hardness is verified and compared to other published designs via the proposed systematic simulation approach that comprehends multiple node charge collection and tests resiliency to upsets at all internal and input nodes. Comparison of the hardness, as measured by estimated upset cross-section, is made to other published designs. Additionally, the importance of specific circuit design aspects to achieving hardness is shown.
ContributorsShambhulingaiah, Sandeep (Author) / Clark, Lawrence (Thesis advisor) / Holbert, Keith E. (Committee member) / Seo, Jae sun (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2015
Description
Ever reducing time to market, along with short product lifetimes, has created a need to shorten the microprocessor design time. Verification of the design and its analysis are two major components of this design cycle. Design validation techniques can be broadly classified into two major categories: simulation based approaches and formal techniques. Simulation based microprocessor validation involves running millions of cycles using random or pseudo random tests and allows verification of the register transfer level (RTL) model against an architectural model, i.e., that the processor executes instructions as required. The validation effort involves model checking to a high level description or simulation of the design against the RTL implementation. Formal techniques exhaustively analyze parts of the design but, do not verify RTL against the architecture specification. The focus of this work is to implement a fully automated validation environment for a MIPS based radiation hardened microprocessor using simulation based approaches. The basic framework uses the classical validation approach in which the design to be validated is described in a Hardware Definition Language (HDL) such as VHDL or Verilog. To implement a simulation based approach a number of random or pseudo random tests are generated. The output of the HDL based design is compared against the one obtained from a "perfect" model implementing similar functionality, a mismatch in the results would thus indicate a bug in the HDL based design. Effort is made to design the environment in such a manner that it can support validation during different stages of the design cycle. The validation environment includes appropriate changes so as to support architecture changes which are introduced because of radiation hardening. The manner in which the validation environment is build is highly dependent on the specifications of the perfect model used for comparisons. This work implements the validation environment for two MIPS simulators as the reference model. Two bugs have been discovered in the RTL model, using simulation based approaches through the validation environment.
ContributorsSharma, Abhishek (Author) / Clark, Lawrence (Thesis advisor) / Holbert, Keith E. (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2011
Description
Yannis Constantinidis was the last of the handful of composers referred to collectively as the Greek National School. The members of this group strove to create a distinctive national style for Greece, founded upon a synthesis of Western compositional idioms with melodic, rhyhmic, and modal features of their local folk traditions. Constantinidis particularly looked to the folk melodies of his native Asia Minor and the nearby Dodecanese Islands. His musical output includes operettas, musical comedies, orchestral works, chamber and vocal music, and much piano music, all of which draws upon folk repertories for thematic material. The present essay examines how he incorporates this thematic material in his piano compositions, written between 1943 and 1971, with a special focus on the 22 Songs and Dances from the Dodecanese. In general, Constantinidis's pianistic style is expressed through miniature pieces in which the folk tunes are presented mostly intact, but embedded in accompaniment based in early twentieth-century modal harmony. Following the dictates of the founding members of the Greek National School, Manolis Kalomiris and Georgios Lambelet, the modal basis of his harmonic vocabulary is firmly rooted in the characteristics of the most common modes of Greek folk music. A close study of his 22 Songs and Dances from the Dodecanese not only offers a valuable insight into his harmonic imagination, but also demonstrates how he subtly adapts his source melodies. This work also reveals his care in creating a musical expression of the words of the original folk songs, even in purely instrumental compositon.
ContributorsSavvidou, Dina (Author) / Hamilton, Robert (Thesis advisor) / Little, Bliss (Committee member) / Meir, Baruch (Committee member) / Thompson, Janice M (Committee member) / Arizona State University (Publisher)
Created2011
Description
CMOS technology is expected to enter the 10nm regime for future integrated circuits (IC). Such aggressive scaling leads to vastly increased variability, posing a grand challenge to robust IC design. Variations in CMOS are often divided into two types: intrinsic variations and process-induced variations. Intrinsic variations are limited by fundamental physics. They are inherent to CMOS structure, considered as one of the ultimate barriers to the continual scaling of CMOS devices. In this work the three primary intrinsic variations sources are studied, including random dopant fluctuation (RDF), line-edge roughness (LER) and oxide thickness fluctuation (OTF). The research is focused on the modeling and simulation of those variations and their scaling trends. Besides the three variations, a time dependent variation source, Random Telegraph Noise (RTN) is also studied. Different from the other three variations, RTN does not contribute much to the total variation amount, but aggregate the worst case of Vth variations in CMOS. In this work a TCAD based simulation study on RTN is presented, and a new SPICE based simulation method for RTN is proposed for time domain circuit analysis. Process-induced variations arise from the imperfection in silicon fabrication, and vary from foundries to foundries. In this work the layout dependent Vth shift due to Rapid-Thermal Annealing (RTA) are investigated. In this work, we develop joint thermal/TCAD simulation and compact modeling tools to analyze performance variability under various layout pattern densities and RTA conditions. Moreover, we propose a suite of compact models that bridge the underlying RTA process with device parameter change for efficient design optimization.
ContributorsYe, Yun, Ph.D (Author) / Cao, Yu (Thesis advisor) / Yu, Hongbin (Committee member) / Song, Hongjiang (Committee member) / Clark, Lawrence (Committee member) / Arizona State University (Publisher)
Created2011