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Description
Dynamic loading is the term used for one way of optimally loading a transformer. Dynamic loading means the utility takes into account the thermal time constant of the transformer along with the cooling mode transitions, loading profile and ambient temperature when determining the time-varying loading capability of a transformer. Knowing

Dynamic loading is the term used for one way of optimally loading a transformer. Dynamic loading means the utility takes into account the thermal time constant of the transformer along with the cooling mode transitions, loading profile and ambient temperature when determining the time-varying loading capability of a transformer. Knowing the maximum dynamic loading rating can increase utilization of the transformer while not reducing life-expectancy, delaying the replacement of the transformer. This document presents the progress on the transformer dynamic loading project sponsored by Salt River Project (SRP). A software application which performs dynamic loading for substation distribution transformers with appropriate transformer thermal models is developed in this project. Two kinds of thermal hottest-spot temperature (HST) and top-oil temperature (TOT) models that will be used in the application--the ASU HST/TOT models and the ANSI models--are presented. Brief validations of the ASU models are presented, showing that the ASU models are accurate in simulating the thermal processes of the transformers. For this production grade application, both the ANSI and the ASU models are built and tested to select the most appropriate models to be used in the dynamic loading calculations. An existing application to build and select the TOT model was used as a starting point for the enhancements developed in this work. These enhancements include:  Adding the ability to develop HST models to the existing application,  Adding metrics to evaluate the models accuracy and selecting which model will be used in dynamic loading calculation  Adding the capability to perform dynamic loading calculations,  Production of a maximum dynamic load profile that the transformer can tolerate without acceleration of the insulation aging,  Provide suitable output (plots and text) for the results of the dynamic loading calculation. Other challenges discussed include: modification to the input data format, data-quality control, cooling mode estimation. Efforts to overcome these challenges are discussed in this work.
ContributorsLiu, Yi (Author) / Tylavksy, Daniel J (Thesis advisor) / Karady, George G. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2011
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Description
In this thesis, a Built-in Self Test (BiST) based testing solution is proposed to measure linear and non-linear impairments in the RF Transmitter path using analytical approach. Design issues and challenges with the impairments modeling and extraction in transmitter path are discussed. Transmitter is modeled for I/Q gain & phase

In this thesis, a Built-in Self Test (BiST) based testing solution is proposed to measure linear and non-linear impairments in the RF Transmitter path using analytical approach. Design issues and challenges with the impairments modeling and extraction in transmitter path are discussed. Transmitter is modeled for I/Q gain & phase mismatch, system non-linearity and DC offset using Matlab. BiST architecture includes a peak detector which includes a self mode mixer and 200 MHz filter. Self Mode mixing operation with filtering removes the high frequency signal contents and allows performing analysis on baseband frequency signals. Transmitter impairments were calculated using spectral analysis of output from the BiST circuitry using an analytical method. Matlab was used to simulate the system with known test impairments and impairment values from simulations were calculated based on system modeling in Mathematica. Simulated data is in good correlation with input test data along with very fast test time and high accuracy. The key contribution of the work is that, system impairments are extracted from transmitter response at baseband frequency using envelope detector hence eliminating the need of expensive high frequency ATE (Automated Test Equipments).
ContributorsGoyal, Nitin (Author) / Ozev, Sule (Thesis advisor) / Duman, Tolga (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
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Description
A numerical study of incremental spin-up and spin-up from rest of a thermally- stratified fluid enclosed within a right circular cylinder with rigid bottom and side walls and stress-free upper surface is presented. Thermally stratified spin-up is a typical example of baroclinity, which is initiated by a sudden increase in

A numerical study of incremental spin-up and spin-up from rest of a thermally- stratified fluid enclosed within a right circular cylinder with rigid bottom and side walls and stress-free upper surface is presented. Thermally stratified spin-up is a typical example of baroclinity, which is initiated by a sudden increase in rotation rate and the tilting of isotherms gives rise to baroclinic source of vorticity. Research by (Smirnov et al. [2010a]) showed the differences in evolution of instabilities when Dirichlet and Neumann thermal boundary conditions were applied at top and bottom walls. Study of parametric variations carried out in this dissertation confirmed the instability patterns observed by them for given aspect ratio and Rossby number values greater than 0.5. Also results reveal that flow maintained axisymmetry and stability for short aspect ratio containers independent of amount of rotational increment imparted. Investigation on vorticity components provides framework for baroclinic vorticity feedback mechanism which plays important role in delayed rise of instabilities when Dirichlet thermal Boundary Conditions are applied.
ContributorsKher, Aditya Deepak (Author) / Chen, Kangping (Thesis advisor) / Huang, Huei-Ping (Committee member) / Herrmann, Marcus (Committee member) / Arizona State University (Publisher)
Created2011
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Description
Recent changes in the energy markets structure combined with the conti-nuous load growth have caused power systems to be operated under more stressed conditions. In addition, the nature of power systems has also grown more complex and dynamic because of the increasing use of long inter-area tie-lines and the high

Recent changes in the energy markets structure combined with the conti-nuous load growth have caused power systems to be operated under more stressed conditions. In addition, the nature of power systems has also grown more complex and dynamic because of the increasing use of long inter-area tie-lines and the high motor loads especially those comprised mainly of residential single phase A/C motors. Therefore, delayed voltage recovery, fast voltage collapse and short term voltage stability issues in general have obtained significant importance in relia-bility studies. Shunt VAr injection has been used as a countermeasure for voltage instability. However, the dynamic and fast nature of short term voltage instability requires fast and sufficient VAr injection, and therefore dynamic VAr devices such as Static VAr Compensators (SVCs) and STATic COMpensators (STAT-COMs) are used. The location and size of such devices are optimized in order to improve their efficiency and reduce initial costs. In this work time domain dy-namic analysis was used to evaluate trajectory voltage sensitivities for each time step. Linear programming was then performed to determine the optimal amount of required VAr injection at each bus, using voltage sensitivities as weighting factors. Optimal VAr injection values from different operating conditions were weighted and averaged in order to obtain a final setting of the VAr requirement. Some buses under consideration were either assigned very small VAr injection values, or not assigned any value at all. Therefore, the approach used in this work was found to be useful in not only determining the optimal size of SVCs, but also their location.
ContributorsSalloum, Ahmed (Author) / Vittal, Vijay (Thesis advisor) / Heydt, Gerald (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2011
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Description
Image processing in canals, rivers and other bodies of water has been a very important concern. This research using Image Processing was performed to obtain a photographic evidence of the data of the site which helps in monitoring the conditions of the water body and the surroundings. Images are captured

Image processing in canals, rivers and other bodies of water has been a very important concern. This research using Image Processing was performed to obtain a photographic evidence of the data of the site which helps in monitoring the conditions of the water body and the surroundings. Images are captured using a digital camera and the images are stored onto a datalogger, these images are retrieved using a cellular/ satellite modem. A MATLAB program was designed to obtain the level of water by just entering the file name into to the program, a curve fit model was created to determine the contrast parameters. The contrast parameters were obtained using the data obtained from the gray scale image mainly the mean and variance of the intensity values. The enhanced images are used to determine the level of water by taking pixel intensity plots along the region of interest. The level of water obtained is accurate to less than 2% of the actual level of water observed from the image. High speed imaging in micro channels have various application in industrial field, medical field etc. In medical field it is tested by using blood samples. The experimental procedure proposed determines the flow duration and the defects observed in these channel using a fluid introduced into the micro channel the fluid being water based dye and whole milk. The viscosity of the fluid shows different types of flow patterns and defects in the micro channel. The defects observed vary from a small effect to the flow pattern to an extreme defect in the channel such as obstruction of flow or deformation in the channel. The sample needs to be further analyzed by SEM to get a better insight on the defects.
ContributorsShasedhara, Abhijeet Bangalore (Author) / Lee, Taewoo (Thesis advisor) / Huang, Huei-Ping (Committee member) / Chen, Kangping (Committee member) / Arizona State University (Publisher)
Created2011
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Description
Redundant Binary (RBR) number representations have been extensively used in the past for high-throughput Digital Signal Processing (DSP) systems. Data-path components based on this number system have smaller critical path delay but larger area compared to conventional two's complement systems. This work explores the use of RBR number representation for

Redundant Binary (RBR) number representations have been extensively used in the past for high-throughput Digital Signal Processing (DSP) systems. Data-path components based on this number system have smaller critical path delay but larger area compared to conventional two's complement systems. This work explores the use of RBR number representation for implementing high-throughput DSP systems that are also energy-efficient. Data-path components such as adders and multipliers are evaluated with respect to critical path delay, energy and Energy-Delay Product (EDP). A new design for a RBR adder with very good EDP performance has been proposed. The corresponding RBR parallel adder has a much lower critical path delay and EDP compared to two's complement carry select and carry look-ahead adder implementations. Next, several RBR multiplier architectures are investigated and their performance compared to two's complement systems. These include two new multiplier architectures: a purely RBR multiplier where both the operands are in RBR form, and a hybrid multiplier where the multiplicand is in RBR form and the other operand is represented in conventional two's complement form. Both the RBR and hybrid designs are demonstrated to have better EDP performance compared to conventional two's complement multipliers. The hybrid multiplier is also shown to have a superior EDP performance compared to the RBR multiplier, with much lower implementation area. Analysis on the effect of bit-precision is also performed, and it is shown that the performance gain of RBR systems improves for higher bit precision. Next, in order to demonstrate the efficacy of the RBR representation at the system-level, the performance of RBR and hybrid implementations of some common DSP kernels such as Discrete Cosine Transform, edge detection using Sobel operator, complex multiplication, Lifting-based Discrete Wavelet Transform (9, 7) filter, and FIR filter, is compared with two's complement systems. It is shown that for relatively large computation modules, the RBR to two's complement conversion overhead gets amortized. In case of systems with high complexity, for iso-throughput, both the hybrid and RBR implementations are demonstrated to be superior with lower average energy consumption. For low complexity systems, the conversion overhead is significant, and overpowers the EDP performance gain obtained from the RBR computation operation.
ContributorsMahadevan, Rupa (Author) / Chakrabarti, Chaitali (Thesis advisor) / Kiaei, Sayfe (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2011
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Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices

ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
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Description
All-dielectric self-supporting (ADSS) fiber optic cables are used for data transfer by the utilities. They are installed along high voltage transmission lines. Dry band arcing, a phenomenon which is observed in outdoor insulators, is also observed in ADSS cables. The heat developed during dry band arcing damages the ADSS cables'

All-dielectric self-supporting (ADSS) fiber optic cables are used for data transfer by the utilities. They are installed along high voltage transmission lines. Dry band arcing, a phenomenon which is observed in outdoor insulators, is also observed in ADSS cables. The heat developed during dry band arcing damages the ADSS cables' outer sheath. A method is presented here to rate the cable sheath using the power developed during dry band arcing. Because of the small diameter of ADSS cables, mechanical vibration is induced in ADSS cable. In order to avoid damage, vibration dampers known as spiral vibration dampers (SVD) are used over these ADSS cables. These dampers are installed near the armor rods, where the presence of leakage current and dry band activity is more. The effect of dampers on dry band activity is investigated by conducting experiments on ADSS cable and dampers. Observations made from the experiments suggest that the hydrophobicity of the cable and damper play a key role in stabilizing dry band arcs. Hydrophobic-ity of the samples have been compared. The importance of hydrophobicity of the samples is further illustrated with the help of simulation results. The results indi-cate that the electric field increases at the edges of water strip. The dry band arc-ing phenomenon could thus be correlated to the hydrophobicity of the outer sur-face of cable and damper.
ContributorsPrabakar, Kumaraguru (Author) / Karady, George G. (Thesis advisor) / Vittal, Vijay (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2011
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Description
The evolution of single hairpin vortices and multiple interacting hairpin vortices are studied in direct numerical simulations of channel flow at Re-tau=395. The purpose of this study is to observe the effects of increased Reynolds number and varying initial conditions on the growth of hairpins and the conditions under which

The evolution of single hairpin vortices and multiple interacting hairpin vortices are studied in direct numerical simulations of channel flow at Re-tau=395. The purpose of this study is to observe the effects of increased Reynolds number and varying initial conditions on the growth of hairpins and the conditions under which single hairpins autogenerate hairpin packets. The hairpin vortices are believed to provide a unified picture of wall turbulence and play an important role in the production of Reynolds shear stress which is directly related to turbulent drag. The structures of the initial three-dimensional vortices are extracted from the two-point spatial correlation of the fully turbulent direct numerical simulation of the velocity field by linear stochastic estimation and embedded in a mean flow having the profile of the fully turbulent flow. The Reynolds number of the present simulation is more than twice that of the Re-tau=180 flow from earlier literature and the conditional events used to define the stochastically estimated single vortex initial conditions include a number of new types of events such as quasi-streamwise vorticity and Q4 events. The effects of parameters like strength, asymmetry and position are evaluated and compared with existing results in the literature. This study then attempts to answer questions concerning how vortex mergers produce larger scale structures, a process that may contribute to the growth of length scale with increasing distance from the wall in turbulent wall flows. Multiple vortex interactions are studied in detail.
ContributorsParthasarathy, Praveen Kumar (Author) / Adrian, Ronald (Thesis advisor) / Huang, Huei-Ping (Committee member) / Herrmann, Marcus (Committee member) / Arizona State University (Publisher)
Created2011
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Description
The high penetration of photovoltaic (PV) both at the utility and at the distribu-tion levels, has raised concerns about the reliability of grid-tied inverters of PV power systems. Inverters are generally considered as the weak link in PV power systems. The lack of a dedicated qualification/reliability standard for PV inverters

The high penetration of photovoltaic (PV) both at the utility and at the distribu-tion levels, has raised concerns about the reliability of grid-tied inverters of PV power systems. Inverters are generally considered as the weak link in PV power systems. The lack of a dedicated qualification/reliability standard for PV inverters is a main barrier in realizing higher level of confidence in reliability. Development of a well-accepted design qualification standard specifically for PV inverters will help pave the way for significant improvement in reliability and performance of inverters across the entire industry. The existing standards for PV inverters such as UL 1741 and IEC 62109-1 primarily focus on safety. IEC 62093 discusses inverter qualification but it includes all the balance of sys-tem components and therefore not specific to PV inverters. There are other general stan-dards for distributed generators including the IEEE1547 series of standards which cover major concerns like utility integration but they are not dedicated to PV inverters and are not written from a design qualification point of view. In this thesis, some of the potential requirements for a design qualification standard for PV inverters are addressed. The IEC 62093 is considered as a guideline and the possible inclusions in the framework for a dedicated design qualification standard of PV inverter are discussed. The missing links in existing PV inverter related standards are identified by performing gap analysis. Dif-ferent requirements of small residential inverters compared to large utility-scale systems, and the emerging requirements on grid support features are also considered. Electric stress test is found to be the key missing link and one of the electric stress tests, the surge withstand test is studied in detail. The use of the existing standards for surge withstand test of residential scale PV inverters is investigated and a method to suitably adopt these standards is proposed. The proposed method is studied analytically and verified using simulation. A design criterion for choosing the switch ratings of the inverter that can per-form reliably under the surge environment is derived.
ContributorsAlampoondi Venkataramanan, Sai Balasubramanian (Author) / Ayyanar, Raja (Thesis advisor) / Vittal, Vijay (Committee member) / Heydt, Gerald (Committee member) / Arizona State University (Publisher)
Created2011