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- Genre: Masters Thesis
Description
The photovoltaic systems used to convert solar energy to electricity pose a multitude of design and implementation challenges, including energy conversion efficiency, partial shading effects, and power converter efficiency. Using power converters for Distributed Maximum Power Point Tracking (DMPPT) is a well-known architecture to significantly reduce power loss associated with mismatched panels. Sub-panel-level DMPPT is shown to have up to 14.5% more annual energy yield than panel-level DMPPT, and requires an efficient medium power converter.
This research aims at implementing a highly efficient power management system at sub-panel level with focus on system cost and form-factor. Smaller form-factor motivates increased converter switching frequencies to significantly reduce the size of converter passives and substantially improve transient performance. But, currently available power MOSFETs put a constraint on the highest possible switching frequency due to increased switching losses. The solution is Gallium Nitride based power devices, which deliver figure of merit (FOM) performance at least an order of magnitude higher than existing silicon MOSFETs. Low power loss, high power density, low cost and small die sizes are few of the qualities that make e-GaN superior to its Si counterpart. With careful design, e-GaN can enable a 20-30% improvement in power stage efficiency compared to converters using Si MOSFETs.
The main objective of this research is to develop a highly integrated, high efficiency, 20MHz, hybrid GaN-CMOS DC-DC MPPT converter for a 12V/5A sub-panel. Hard and soft switching boost converter topologies are investigated within this research, and an innovative CMOS gate drive technique for efficiently driving an e-GaN power stage is presented in this work. The converter controller also employs a fast converging analog MPPT control technique.
This research aims at implementing a highly efficient power management system at sub-panel level with focus on system cost and form-factor. Smaller form-factor motivates increased converter switching frequencies to significantly reduce the size of converter passives and substantially improve transient performance. But, currently available power MOSFETs put a constraint on the highest possible switching frequency due to increased switching losses. The solution is Gallium Nitride based power devices, which deliver figure of merit (FOM) performance at least an order of magnitude higher than existing silicon MOSFETs. Low power loss, high power density, low cost and small die sizes are few of the qualities that make e-GaN superior to its Si counterpart. With careful design, e-GaN can enable a 20-30% improvement in power stage efficiency compared to converters using Si MOSFETs.
The main objective of this research is to develop a highly integrated, high efficiency, 20MHz, hybrid GaN-CMOS DC-DC MPPT converter for a 12V/5A sub-panel. Hard and soft switching boost converter topologies are investigated within this research, and an innovative CMOS gate drive technique for efficiently driving an e-GaN power stage is presented in this work. The converter controller also employs a fast converging analog MPPT control technique.
ContributorsKrishnan Achary, Kiran Kumar (Author) / Kitchen, Jennifer (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2015
Description
This thesis presents efficient implementations of several linear algebra kernels, machine learning kernels and a neural network based recommender systems engine onto a massively parallel reconfigurable architecture, Transformer. The linear algebra kernels include Triangular Matrix Solver (TRSM), LU Decomposition (LUD), QR Decomposition (QRD), and Matrix Inversion. The machine learning kernels include an LSTM (Long Short Term Memory) cell, and a GRU (gated Recurrent Unit) cell used in recurrent neural networks. The neural network based recommender systems engine consists of multiple kernels including fully connected layers, embedding layer, 1-D batchnorm, Adam optimizer, etc.
Transformer is a massively parallel reconfigurable multicore architecture designed at the University of Michigan. The Transformer configuration considered here is 4 tiles and 16 General Processing Elements (GPEs) per tile. It supports a two level cache hierarchy where the L1 and L2 caches can operate in shared (S) or private (P) modes. The architecture was modeled using Gem5 and cycle accurate simulations were done to evaluate the performance in terms of execution times, giga-operations per second per Watt (GOPS/W), and giga-floating-point-operations per second per Watt (GFLOPS/W).
This thesis shows that for linear algebra kernels, each kernel achieves high performance for a certain cache mode and that this cache mode can change when the matrix size changes. For instance, for smaller matrix sizes, L1P, L2P cache mode is best for TRSM, while L1S, L2S is the best cache mode for LUD, and L1P, L2S is the best for QRD. For each kernel, the optimal cache mode changes when the matrix size is increased. For instance, for TRSM, the L1P, L2P cache mode is best for smaller matrix sizes ($N=64, 128, 256, 512$) and it changes to L1S, L2P for larger matrix sizes ($N=1024$). For machine learning kernels, L1P, L2P is the best cache mode for all network parameter sizes.
Gem5 simulations show that the peak performance for TRSM, LUD, QRD and Matrix Inverse in the 14nm node is 97.5, 59.4, 133.0 and 83.05 GFLOPS/W, respectively. For LSTM and GRU, the peak performance is 44.06 and 69.3 GFLOPS/W.
The neural network based recommender system was implemented in L1S, L2S cache mode. It includes a forward pass and a backward pass and is significantly more complex in terms of both computational complexity and data movement. The most computationally intensive block is the fully connected layer followed by Adam optimizer. The overall performance of the recommender systems engine is 54.55 GFLOPS/W and 169.12 GOPS/W.
Transformer is a massively parallel reconfigurable multicore architecture designed at the University of Michigan. The Transformer configuration considered here is 4 tiles and 16 General Processing Elements (GPEs) per tile. It supports a two level cache hierarchy where the L1 and L2 caches can operate in shared (S) or private (P) modes. The architecture was modeled using Gem5 and cycle accurate simulations were done to evaluate the performance in terms of execution times, giga-operations per second per Watt (GOPS/W), and giga-floating-point-operations per second per Watt (GFLOPS/W).
This thesis shows that for linear algebra kernels, each kernel achieves high performance for a certain cache mode and that this cache mode can change when the matrix size changes. For instance, for smaller matrix sizes, L1P, L2P cache mode is best for TRSM, while L1S, L2S is the best cache mode for LUD, and L1P, L2S is the best for QRD. For each kernel, the optimal cache mode changes when the matrix size is increased. For instance, for TRSM, the L1P, L2P cache mode is best for smaller matrix sizes ($N=64, 128, 256, 512$) and it changes to L1S, L2P for larger matrix sizes ($N=1024$). For machine learning kernels, L1P, L2P is the best cache mode for all network parameter sizes.
Gem5 simulations show that the peak performance for TRSM, LUD, QRD and Matrix Inverse in the 14nm node is 97.5, 59.4, 133.0 and 83.05 GFLOPS/W, respectively. For LSTM and GRU, the peak performance is 44.06 and 69.3 GFLOPS/W.
The neural network based recommender system was implemented in L1S, L2S cache mode. It includes a forward pass and a backward pass and is significantly more complex in terms of both computational complexity and data movement. The most computationally intensive block is the fully connected layer followed by Adam optimizer. The overall performance of the recommender systems engine is 54.55 GFLOPS/W and 169.12 GOPS/W.
ContributorsSoorishetty, Anuraag (Author) / Chakrabarti, Chaitali (Thesis advisor) / Kim, Hun Seok (Committee member) / LiKamWa, Robert (Committee member) / Arizona State University (Publisher)
Created2019
Description
State-of-the-art automotive radars use multi-chip Frequency Modulated Continuous Wave (FMCW) radars to sense the environment around the car. FMCW radars are prone to interference as they operate over a narrow baseband bandwidth and use similar radio frequency (RF) chirps among them. Phase Modulated Continuous Wave radars (PMCW) are robust and insensitive to interference as they transmit signals over a wider bandwidth using spread spectrum technique. As more and more cars are equipped with FMCW radars illuminate the same environment, interference would soon become a serious issue. PMCW radars can be an effective solution to interference in the noisy FMCW radar environment. PMCW radars can be implemented in silicon as System-on-a-chip (SoC), suitable for Multiple-Input-Multiple-Output (MIMO) implementation and is highly programmable. PMCW radars do not require highly linear high frequency chirping oscillators thus reducing the size of the final solution.
This thesis aims to present a behavior model for this promising Digitally modulated radar (DMR) transceiver in Simulink/Matlab. The goal of this work is to create a model for the electronic system level framework that simulates the entire system with non-idealities. This model includes a Top Down Design methodology to understand the requirements of the individual modules’ performance and thus derive the specifications for implementing the real chip. Back annotation of the actual electrical modules’ performance to the model closes the design process loop. Using Simulink’s toolboxes, a passband and equivalent baseband model of the system is built for the transceiver with non-idealities of the components built in along with signal processing routines in Matlab. This model provides a platform for system evaluation and simulation for various system scenarios and use-cases of sensing using the environment around a moving car.
This thesis aims to present a behavior model for this promising Digitally modulated radar (DMR) transceiver in Simulink/Matlab. The goal of this work is to create a model for the electronic system level framework that simulates the entire system with non-idealities. This model includes a Top Down Design methodology to understand the requirements of the individual modules’ performance and thus derive the specifications for implementing the real chip. Back annotation of the actual electrical modules’ performance to the model closes the design process loop. Using Simulink’s toolboxes, a passband and equivalent baseband model of the system is built for the transceiver with non-idealities of the components built in along with signal processing routines in Matlab. This model provides a platform for system evaluation and simulation for various system scenarios and use-cases of sensing using the environment around a moving car.
ContributorsKalyan, Prassana (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Thesis advisor) / Garrity, Douglas (Committee member) / Arizona State University (Publisher)
Created2019
Description
Power management circuits are employed in most electronic integrated systems, including applications for automotive, IoT, and smart wearables. Oftentimes, these power management circuits become a single point of system failure, and since they are present in most modern electronic devices, they become a target for hardware security attacks. Digital circuits are typically more prone to security attacks compared to analog circuits, but malfunctions in digital circuitry can affect the analog performance/parameters of power management circuits. This research studies the effect that these hacks will have on the analog performance of power circuits, specifically linear and switching power regulators/converters. Apart from security attacks, these circuits suffer from performance degradations due to temperature, aging, and load stress. Power management circuits usually consist of regulators or converters that regulate the load’s voltage supply by employing a feedback loop, and the stability of the feedback loop is a critical parameter in the system design. Oftentimes, the passive components employed in these circuits shift in value over varying conditions and may cause instability within the power converter. Therefore, variations in the passive components, as well as malicious hardware security attacks, can degrade regulator performance and affect the system’s stability. The traditional ways of detecting phase margin, which indicates system stability, employ techniques that require the converter to be in open loop, and hence can’t be used while the system is deployed in-the-field under normal operation. Aging of components and security attacks may occur after the power management systems have completed post-production test and have been deployed, and they may not cause catastrophic failure of the system, hence making them difficult to detect. These two issues of component variations and security attacks can be detected during normal operation over the product lifetime, if the frequency response of the power converter can be monitored in-situ and in-field. This work presents a method to monitor the phase margin (stability) of a power converter without affecting its normal mode of operation by injecting a white noise/ pseudo random binary sequence (PRBS). Furthermore, this work investigates the analog performance parameters, including phase margin, that are affected by various digital hacks on the control circuitry associated with power converters. A case study of potential hardware attacks is completed for a linear low-dropout regulator (LDO).
ContributorsMalakar, Pragya Priya (Author) / Kitchen, Jennifer (Thesis advisor) / Ozev, Sule (Committee member) / Brunhaver, John (Committee member) / Arizona State University (Publisher)
Created2019
Description
The efficiency of spacecraft’s solar cells reduces over the course of their operation. Traditionally, they are configured to extract maximum power at the end of their life and not have a system which dynamically extracts the maximum power over their entire life. This work demonstrates the benefit of dynamic re-configuration of spacecraft’s solar arrays to access the full power available from the solar panels throughout their lifetime. This dynamic re-configuration is achieved using enhancement mode GaN devices as the switches due to their low Ron and small footprint.
This work discusses hardware Implementation challenges and a prototype board is designed using components-off-the-shelf (COTS) to study the behavior of photovoltaic (PV) panels with different configurations of switches between 5 PV cells. The measurement results from the board proves the feasibility of the idea, showing the power improvements of having the switch structure. The measurement results are used to simulate a 1kW satellite system and understand practical trade-offs of this idea in actual satellite power systems.
Additionally, this work also presents the implementation of CMOS controller integrated circuit (IC) in 0.18um technology. The CMOS controller IC includes switched-capacitor converters in open loop to provide the floating voltages required to drive the GaN switches. Each CMOS controller IC can drive 10 switches in series and parallel combination. Furthermore, the designed controller IC is expected to operate under 300MRad of total dose radiation, thus enabling the controller modules to be placed on the solar cell wings of the satellites.
This work discusses hardware Implementation challenges and a prototype board is designed using components-off-the-shelf (COTS) to study the behavior of photovoltaic (PV) panels with different configurations of switches between 5 PV cells. The measurement results from the board proves the feasibility of the idea, showing the power improvements of having the switch structure. The measurement results are used to simulate a 1kW satellite system and understand practical trade-offs of this idea in actual satellite power systems.
Additionally, this work also presents the implementation of CMOS controller integrated circuit (IC) in 0.18um technology. The CMOS controller IC includes switched-capacitor converters in open loop to provide the floating voltages required to drive the GaN switches. Each CMOS controller IC can drive 10 switches in series and parallel combination. Furthermore, the designed controller IC is expected to operate under 300MRad of total dose radiation, thus enabling the controller modules to be placed on the solar cell wings of the satellites.
ContributorsHeblikar, Anand N (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2019
Description
Point of Load (POL) DC-DC converters are increasingly used in space applications, data centres, electric vehicles, portable computers and devices and medical electronics. Heavy computing and processing capabilities of the modern devices have ushered the use of higher battery supply voltage to increase power storage. The need to address this consumer experience driven requirement has propelled the evolution of the next generation of small form-factor power converters which can operate with higher step down ratios while supplying heavy continuous load currents without sacrificing efficiency. Constant On-Time (COT) converter topology is capable of achieving stable operation at high conversion ratio with minimum off-chip components and small silicon area. This work proposes a Constant On-Time buck dc-dc converter for a wide dynamic input range and load currents from 100mA to 10A. Accuracy of this ripple based converter is improved by a unique voltage positioning technique which modulates the reference voltage to lower the average ripple profile close to the nominal output. Adaptive On-time block features a transient enhancement scheme to assist in faster voltage droop recovery when the output voltage dips below a defined threshold. UtilizingGallium Nitride (GaN) power switches enable the proposed converter to achieve very high efficiency while using smaller size inductor-capacitor (LC) power-stage. Use of novel Superjunction devices with higher drain-source blocking voltage simplifies the complex driver design and enables faster frequency of operation. It allows 1.8VComplementary Metal-Oxide Semiconductor (CMOS) devices to effectively drive GaNpower FETs which require 5V gate signal swing. The presented controller circuit uses internal ripple generation which reduces reliance on output cap equivalent series resistance (ESR) for loop stability and facilitates ripples reduction at the output. The ripple generation network is designed to provide ai
optimally stable performance while maintaining load regulation and line regulation accuracy withing specified margin. The chip with ts external Power FET package is proposed to be integrated on a printed circuit board for testing. The designed power converter is expected to operate under 200 MRad of a total ionising dose of radiation enabling it to function within large hadron collider at CERN and space satellite and probe missions.
optimally stable performance while maintaining load regulation and line regulation accuracy withing specified margin. The chip with ts external Power FET package is proposed to be integrated on a printed circuit board for testing. The designed power converter is expected to operate under 200 MRad of a total ionising dose of radiation enabling it to function within large hadron collider at CERN and space satellite and probe missions.
ContributorsJoshi, Omkar (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Long, Yu (Committee member) / Arizona State University (Publisher)
Created2019
Description
This work analyzes and develops a point-of-load (PoL) synchronous buck converter using enhancement-mode Gallium Nitride (e-GaN), with emphasis on optimizing reverse conduction loss by using a well-known technique of placing an anti-parallel Schottky diode across the synchronous power device. This work develops an improved analytical switching model for the GaN-based converter with the Schottky diode using piecewise linear approximations.
To avoid a shoot-through between the power switches of the buck converter, a small dead-time is inserted between gate drive switching transitions. Despite optimum dead-time management for a power converter, optimum dead-times vary for different load conditions. These variations become considerably large for PoL applications, which demand high output current with low output voltages. At high switching frequencies, these variations translate into losses that contribute significantly to the total loss of the converter. To understand and quantify power loss in a hard-switching buck converter that uses a GaN power device in parallel with a Schottky diode, piecewise transitions are used to develop an analytical switching model that quantifies the contribution of reverse conduction loss of GaN during dead-time.
The effects of parasitic elements on the dynamics of the switching converter are investigated during one switching cycle of the converter. A designed prototype of a buck converter is correlated to the predicted model to determine the accuracy of the model. This comparison is presented using simulations and measurements at 400 kHz and 2 MHz converter switching speeds for load (1A) condition and fixed dead-time values. Furthermore, performance of the buck converter with and without the Schottky diode is also measured and compared to demonstrate and quantify the enhanced performance when using an anti-parallel diode. The developed power converter achieves peak efficiencies of 91.7% and 93.86% for 2 MHz and 400 KHz switching frequencies, respectively, and drives load currents up to 6A for a voltage conversion from 12V input to 3.3V output.
In addition, various industry Schottky diodes have been categorized based on their packaging and electrical characteristics and the developed analytical model provides analytical expressions relating the diode characteristics to power stage performance parameters. The performance of these diodes has been characterized for different buck converter voltage step-down ratios that are typically used in industry applications and different switching frequencies ranging from 400 KHz to 2 MHz.
To avoid a shoot-through between the power switches of the buck converter, a small dead-time is inserted between gate drive switching transitions. Despite optimum dead-time management for a power converter, optimum dead-times vary for different load conditions. These variations become considerably large for PoL applications, which demand high output current with low output voltages. At high switching frequencies, these variations translate into losses that contribute significantly to the total loss of the converter. To understand and quantify power loss in a hard-switching buck converter that uses a GaN power device in parallel with a Schottky diode, piecewise transitions are used to develop an analytical switching model that quantifies the contribution of reverse conduction loss of GaN during dead-time.
The effects of parasitic elements on the dynamics of the switching converter are investigated during one switching cycle of the converter. A designed prototype of a buck converter is correlated to the predicted model to determine the accuracy of the model. This comparison is presented using simulations and measurements at 400 kHz and 2 MHz converter switching speeds for load (1A) condition and fixed dead-time values. Furthermore, performance of the buck converter with and without the Schottky diode is also measured and compared to demonstrate and quantify the enhanced performance when using an anti-parallel diode. The developed power converter achieves peak efficiencies of 91.7% and 93.86% for 2 MHz and 400 KHz switching frequencies, respectively, and drives load currents up to 6A for a voltage conversion from 12V input to 3.3V output.
In addition, various industry Schottky diodes have been categorized based on their packaging and electrical characteristics and the developed analytical model provides analytical expressions relating the diode characteristics to power stage performance parameters. The performance of these diodes has been characterized for different buck converter voltage step-down ratios that are typically used in industry applications and different switching frequencies ranging from 400 KHz to 2 MHz.
ContributorsKoli, Gauri (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2020
Description
This work presents two balanced power amplifier (PA) architectures, one at X-band and the other at K-band. The presented balanced PAs are designed for use in small satellite and cube satellite applications.The presented X-band PA employs wideband hybrid couplers to split input power to two commercial off-the-shelf (COTS) Gallium Nitride (GaN) monolithic microwave integrated circuit (MMIC) PAs and combine their output powers. The presented X-band balanced PA manufactured on a Rogers 4003C substrate yields increased small signal gain and saturated output power under continuous wave (CW) operation compared to the single MMIC PA used in the design under pulsed operation. The presented PA operates from 7.5 GHz to 11.5 GHz, has a maximum small signal gain of 36.3 dB, a maximum saturated power out of 40.0 dBm, and a maximum power added efficiency (PAE) of 38%.
Both a Wilkinson and a Gysel splitter and combiner are designed for use at K-band and their performance is compared. The presented K-band balanced PA uses Gysel power dividers and combiners with a GaN MMIC PA that is soon to be released in production.
ContributorsPearson, Katherine Elizabeth (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2023
Description
Kuwait is committed to implementing the Kyoto Protocol in “Vision 2035” to reduce greenhouse gas emissions by shifting to the use of wind and solar energies [1]. The specific goal of the Vision 2035 is for renewables to comprise 15% of Kuwait’s electrical generation by 2030. Wind and solar are abundant in Kuwait and can easily provide 15% of the total electrical generation. However, there are three significant obstacles. The first is Kuwait currently depends heavily on rapidly diminishing fossil fuels which are the major sources of CO2, NOx, and SOx emissions. Unfortunately, current plans are to build two conventional power stations by 2024. The purpose is to cover the energy needs for growing population. The second problem is that Kuwait has a very small land area. Consequently, there is limited space to build new utility-scale renewable power stations. The third issue is the low electricity tariff provides little incentive for the population to save energy. Offshore wind farms have the potential to provide thousands of GWh/yr to accomplish the goals of Vision 2035. Kuwait has a vast untapped supply of offshore wind energy. Specifically, there are eight offshore locations in which 50 turbines could be built each, for a total of 400 turbines. Using 4.2 MW turbines, this would provide 1.68 GW of wind energy, and increase the renewable portion of the electrical energy production to 13.93% (including Shagaya renewable park). Installing battery storage with the proposed wind turbines could provide fast ramp response which would serve to complement existing power production on Kuwait’s grid. In this work, six different turbines with different sizes are considered from 2.5 MW to 4.2 MW (from well-known manufacturers, such as, Nordex and Vestas), but ultimately 4.2 MW turbines are recommended. Data for this study has been supplied by: A) Civil Aviation -- temperature and wind speed, B) Ministry of Electricity and Water (MEW) -- electricity data, and C) Public Authority for Civil Information -- population data.
ContributorsAlotaibi, Abdullah Saqer (Author) / Calhoun, Ronald (Thesis advisor) / Kitchen, Jennifer (Thesis advisor) / Roedel, Ronald (Committee member) / Mayyas, Abdul Ra'ouf (Committee member) / Arizona State University (Publisher)
Created2020