Matching Items (187)
Filtering by
- Genre: Doctoral Dissertation
- Creators: Bakkaloglu, Bertan
- Creators: Gu, Bin
- Member of: ASU Electronic Theses and Dissertations
Description
This article can be divided into six parts.
The first chapter analyzes the background, theatrical and particle reasons of this research. The author argues that the management of law firm needs a set of good system. The first one is operating the law firm in scale, and the other on is corporate management model, which shall be constructed in detail in the paper and will be put into practice by the law firm in which the author is worked.
The second chapter will introduce modern management theory, combining the situation of management in our law firm to analyze, raising some reasonable suggestions and instructions to promote our law firm to achieve the corporate management.
In the third chapter, the first chapter, starting with the review of the development process of foreign and our law firms, listing the organizational forms and the characteristics of our law firm, analyzing the situation and the drawbacks of the law firm management.
The fourth and fifth chapter introduce he background, the connotation of the corporate management model, listing the development and successful experience of some typical cases in respect of corporate management.
In the last chapter, the construction of corporate management model will be introduced in terms of organization form, human resource management and informationizing development.
The corporate management model is not mature in china. Though it is not easy to reform the existing model, but it should be believed that the development benefiting the legal industry will be achieved.
The first chapter analyzes the background, theatrical and particle reasons of this research. The author argues that the management of law firm needs a set of good system. The first one is operating the law firm in scale, and the other on is corporate management model, which shall be constructed in detail in the paper and will be put into practice by the law firm in which the author is worked.
The second chapter will introduce modern management theory, combining the situation of management in our law firm to analyze, raising some reasonable suggestions and instructions to promote our law firm to achieve the corporate management.
In the third chapter, the first chapter, starting with the review of the development process of foreign and our law firms, listing the organizational forms and the characteristics of our law firm, analyzing the situation and the drawbacks of the law firm management.
The fourth and fifth chapter introduce he background, the connotation of the corporate management model, listing the development and successful experience of some typical cases in respect of corporate management.
In the last chapter, the construction of corporate management model will be introduced in terms of organization form, human resource management and informationizing development.
The corporate management model is not mature in china. Though it is not easy to reform the existing model, but it should be believed that the development benefiting the legal industry will be achieved.
ContributorsZhu, Ping (Author) / Gu, Bin (Thesis advisor) / Chang, Chun (Thesis advisor) / Zhu, Ning (Committee member) / Arizona State University (Publisher)
Created2017
Description
Time-interleaved analog to digital converters (ADCs) have become critical components in high-speed communication systems. Consumers demands for smaller size, more bandwidth and more features from their communication systems have driven the market to use modern complementary metal-oxide-semiconductor (CMOS) technologies with shorter channel-length transistors and hence a more compact design. Downscaling the supply voltage which is required in submicron technologies benefits digital circuits in terms of power and area. Designing accurate analog circuits, however becomes more challenging due to the less headroom. One way to overcome this problem is to use calibration to compensate for the loss of accuracy in analog circuits.
Time-interleaving increases the effective data conversion rate in ADCs while keeping the circuit requirements the same. However, this technique needs special considerations as other design issues associated with using parallel identical channels emerge. The first and the most important is the practical issue of timing mismatch between channels, also called sample-time error, which can directly affect the performance of the ADC. Many techniques have been developed to tackle this issue both in analog and digital domains. Most of these techniques have high complexities especially when the number of channels exceeds 2 and some of them are only valid when input signal is a single tone sinusoidal which limits the application.
This dissertation proposes a sample-time error calibration technique which bests the previous techniques in terms of simplicity, and also could be used with arbitrary input signals. A 12-bit 650 MSPS pipeline ADC with 1.5 GHz analog bandwidth for digital beam forming systems is designed in IBM 8HP BiCMOS 130 nm technology. A front-end sample-and-hold amplifier (SHA) was also designed to compare with an SHA-less design in terms of performance, power and area. Simulation results show that the proposed technique is able to improve the SNDR by 20 dB for a mismatch of 50% of the sampling period and up to 29 dB at 37% of the Nyquist frequency. The designed ADC consumes 122 mW in each channel and the clock generation circuit consumes 142 mW. The ADC achieves 68.4 dB SNDR for an input of 61 MHz.
Time-interleaving increases the effective data conversion rate in ADCs while keeping the circuit requirements the same. However, this technique needs special considerations as other design issues associated with using parallel identical channels emerge. The first and the most important is the practical issue of timing mismatch between channels, also called sample-time error, which can directly affect the performance of the ADC. Many techniques have been developed to tackle this issue both in analog and digital domains. Most of these techniques have high complexities especially when the number of channels exceeds 2 and some of them are only valid when input signal is a single tone sinusoidal which limits the application.
This dissertation proposes a sample-time error calibration technique which bests the previous techniques in terms of simplicity, and also could be used with arbitrary input signals. A 12-bit 650 MSPS pipeline ADC with 1.5 GHz analog bandwidth for digital beam forming systems is designed in IBM 8HP BiCMOS 130 nm technology. A front-end sample-and-hold amplifier (SHA) was also designed to compare with an SHA-less design in terms of performance, power and area. Simulation results show that the proposed technique is able to improve the SNDR by 20 dB for a mismatch of 50% of the sampling period and up to 29 dB at 37% of the Nyquist frequency. The designed ADC consumes 122 mW in each channel and the clock generation circuit consumes 142 mW. The ADC achieves 68.4 dB SNDR for an input of 61 MHz.
ContributorsNazari, Ali (Author) / Barnaby, Hugh James (Thesis advisor) / Jalali-Farahani, Bahar (Committee member) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2017
Description
Nearly all solar photovoltaic (PV) systems are designed with maximum power point tracking (MPPT) functionality to maximize the utilization of available power from the PV array throughout the day. In conventional PV systems, the MPPT function is handled by a power electronic device, like a DC-AC inverter. However, given that most PV systems are designed to be grid-connected, there are several challenges for designing PV systems for DC-powered applications and off-grid applications. The first challenge is that all power electronic devices introduce some degree of power loss. Beyond the cost of the lost power, the upfront cost of power electronics also increases with the required power rating. Second, there are very few commercially available options for DC-DC converters that include MPPT functionality, and nearly all PV inverters are designed as “grid-following” devices, as opposed to “grid-forming” devices, meaning they cannot be used in off-grid applications.
To address the challenges of designing PV systems for high-power DC and off-grid applications, a load-managing photovoltaic (LMPV) system topology has been proposed. Instead of using power electronics, the LMPV system performs maximum power point tracking through load management. By implementing a load-management approach, the upfront costs and the power losses associated with the power electronics are avoided, both of which improve the economic viability of the PV system. This work introduces the concept of an LMPV system, provides in-depth analyses through both simulation and experimental validation, and explores several potential applications of the system, such as solar-powered commercial-scale electrolyzers for the production of hydrogen fuel or the production and purification of raw materials like caustic soda, copper, and zinc.
To address the challenges of designing PV systems for high-power DC and off-grid applications, a load-managing photovoltaic (LMPV) system topology has been proposed. Instead of using power electronics, the LMPV system performs maximum power point tracking through load management. By implementing a load-management approach, the upfront costs and the power losses associated with the power electronics are avoided, both of which improve the economic viability of the PV system. This work introduces the concept of an LMPV system, provides in-depth analyses through both simulation and experimental validation, and explores several potential applications of the system, such as solar-powered commercial-scale electrolyzers for the production of hydrogen fuel or the production and purification of raw materials like caustic soda, copper, and zinc.
ContributorsAzzolini, Joseph Anthony (Author) / Tao, Meng (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Qin, Jiangchao (Committee member) / Reno, Matthew J. (Committee member) / Arizona State University (Publisher)
Created2020
Description
The focus of this dissertation is first on understanding the difficulties involved in constructing reduced order models of structures that exhibit a strong nonlinearity/strongly nonlinear events such as snap-through, buckling (local or global), mode switching, symmetry breaking. Next, based on this understanding, it is desired to modify/extend the current Nonlinear Reduced Order Modeling (NLROM) methodology, basis selection and/or identification methodology, to obtain reliable reduced order models of these structures. Focusing on these goals, the work carried out addressed more specifically the following issues:
i) optimization of the basis to capture at best the response in the smallest number of modes,
ii) improved identification of the reduced order model stiffness coefficients,
iii) detection of strongly nonlinear events using NLROM.
For the first issue, an approach was proposed to rotate a limited number of linear modes to become more dominant in the response of the structure. This step was achieved through a proper orthogonal decomposition of the projection on these linear modes of a series of representative nonlinear displacements. This rotation does not expand the modal space but renders that part of the basis more efficient, the identification of stiffness coefficients more reliable, and the selection of dual modes more compact. In fact, a separate approach was also proposed for an independent optimization of the duals. Regarding the second issue, two tuning approaches of the stiffness coefficients were proposed to improve the identification of a limited set of critical coefficients based on independent response data of the structure. Both approaches led to a significant improvement of the static prediction for the clamped-clamped curved beam model. Extensive validations of the NLROMs based on the above novel approaches was carried out by comparisons with full finite element response data. The third issue, the detection of nonlinear events, was finally addressed by building connections between the eigenvalues of the finite element software (Nastran here) and NLROM tangent stiffness matrices and the occurrence of the ‘events’ which is further extended to the assessment of the accuracy with which the NLROM captures the full finite element behavior after the event has occurred.
i) optimization of the basis to capture at best the response in the smallest number of modes,
ii) improved identification of the reduced order model stiffness coefficients,
iii) detection of strongly nonlinear events using NLROM.
For the first issue, an approach was proposed to rotate a limited number of linear modes to become more dominant in the response of the structure. This step was achieved through a proper orthogonal decomposition of the projection on these linear modes of a series of representative nonlinear displacements. This rotation does not expand the modal space but renders that part of the basis more efficient, the identification of stiffness coefficients more reliable, and the selection of dual modes more compact. In fact, a separate approach was also proposed for an independent optimization of the duals. Regarding the second issue, two tuning approaches of the stiffness coefficients were proposed to improve the identification of a limited set of critical coefficients based on independent response data of the structure. Both approaches led to a significant improvement of the static prediction for the clamped-clamped curved beam model. Extensive validations of the NLROMs based on the above novel approaches was carried out by comparisons with full finite element response data. The third issue, the detection of nonlinear events, was finally addressed by building connections between the eigenvalues of the finite element software (Nastran here) and NLROM tangent stiffness matrices and the occurrence of the ‘events’ which is further extended to the assessment of the accuracy with which the NLROM captures the full finite element behavior after the event has occurred.
ContributorsLin, Jinshan (Author) / Mignolet, Marc (Thesis advisor) / Jiang, Hanqing (Committee member) / Oswald, Jay (Committee member) / Spottswood, Stephen (Committee member) / Rajan, Subramaniam D. (Committee member) / Arizona State University (Publisher)
Created2020
Description
Though a single mode of energy transfer, optical radiation meaningfully interacts with its surrounding environment at over a wide range of physical length scales. For this reason, its reconstruction and measurement are of great importance in remote sensing, as these multi-scale interactions encode a great deal of information about distant objects, surfaces, and physical phenomena. For some remote sensing applications, obtaining a desired quantity of interest does not necessitate the explicit mapping of each point in object space to an image space with lenses or mirrors. Instead, only edge rays or physical boundaries of the sensing instrument are considered, while the spatial intensity distribution of optical energy received from a distant object informs its position, optical characteristics, or physical/chemical state.
Admittedly specialized, the principals and consequences of non-imaging optics are nevertheless applicable to heterogeneous semiconductor integration and automotive light detection and ranging (LiDAR), two important emerging technologies. Indeed, a review of relevant engineering literature finds two under-addressed remote sensing challenges. The semiconductor industry lacks an optical strain metrology with displacement resolution smaller than 100 nanometers capable of measuring strain fields between high-density interconnect lines. Meanwhile, little attention is paid to the per-meter sensing characteristics of scene-illuminating flash LiDAR in the context of automotive applications, despite the technology’s much lower cost. It is here that non-imaging optics offers intriguing instrument design and explanations of observed sensor performance at vastly different length scales.
In this thesis, an effective non-contact technique for mapping nanoscale mechanical strain fields and out-of-plane surface warping via laser diffraction is demonstrated, with application as a novel metrology for next-generation semiconductor packages. Additionally, object detection distance of low-cost automotive flash LiDAR, on the order of tens of meters, is understood though principals of optical energy transfer from the surface of a remote object to an extended multi-segment detector. Such information is of consequence when designing an automotive perception system to recognize various roadway objects in low-light scenarios.
Admittedly specialized, the principals and consequences of non-imaging optics are nevertheless applicable to heterogeneous semiconductor integration and automotive light detection and ranging (LiDAR), two important emerging technologies. Indeed, a review of relevant engineering literature finds two under-addressed remote sensing challenges. The semiconductor industry lacks an optical strain metrology with displacement resolution smaller than 100 nanometers capable of measuring strain fields between high-density interconnect lines. Meanwhile, little attention is paid to the per-meter sensing characteristics of scene-illuminating flash LiDAR in the context of automotive applications, despite the technology’s much lower cost. It is here that non-imaging optics offers intriguing instrument design and explanations of observed sensor performance at vastly different length scales.
In this thesis, an effective non-contact technique for mapping nanoscale mechanical strain fields and out-of-plane surface warping via laser diffraction is demonstrated, with application as a novel metrology for next-generation semiconductor packages. Additionally, object detection distance of low-cost automotive flash LiDAR, on the order of tens of meters, is understood though principals of optical energy transfer from the surface of a remote object to an extended multi-segment detector. Such information is of consequence when designing an automotive perception system to recognize various roadway objects in low-light scenarios.
ContributorsHoughton, Todd Kristopher (Author) / Yu, Hongbin (Thesis advisor) / Jiang, Hanqing (Committee member) / Jayasuriya, Suren (Committee member) / Zhang, Liang (Committee member) / Arizona State University (Publisher)
Created2020
Description法律职业全球化作为经济全球化的必然产物，在近二十年来不断受到法律职业社会学者的广泛关注及探讨。中国改革开放四十年中国法律职业得以蓬勃发展，却很少学者研究探讨中国法律职业全球化。在中国企业“走出去”和“一带一路”倡议的背景下，新技术创新特别是人工智能、大数据等浪潮不断冲击着法律职业，给中国法律职业全球化发展带来机遇和挑战。本文拟阐述法律职业发展及其全球化理论，并以比较法视角探索研究不同司法管辖区如美国、英国以及印度等国法律职业全球化经验和启示，考察现有国际律师事务所以及“四大”法律服务全球化的发展历程，并且探新技术的创新是如何改变法律职业、重塑全球法律服务业的格局，通过分析和借鉴法律职业的国际经验、经济学原理和变革趋势探讨中国法律职业改革开放及全球化的模式和路径，并提出相关政策建议
ContributorsChen, Gui (Author) / Gu, Bin (Thesis advisor) / Zhu, Ning (Thesis advisor) / Yan, Hong (Committee member) / Arizona State University (Publisher)
Created2019
Description
A wideband hybrid envelope tracking modulator utilizing a hysteretic-controlled three-level switching converter and a slew-rate enhanced linear amplifierer is presented. In addition to smaller ripple and lower losses of three-level switching converters, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage VCF and eliminates conventional required calibration loop to control it. The hysteretic-controlled three-level switching converter provides a high percentage of power amplifier supply load current with lower ripple, reducing the linear amplifier high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the linear amplifier resulting in slew-rate of
over 307V/us and bandwidth of over 275MHz for the linear amplifier. The slew-rate enhancement circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of out-
put without modifying the operating point of the remaining linear amplifier, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in 65nm CMOS process. The measurement results show the tracking of LTE-40MHz envelope with 93% peak efficiency at 1W output power, while the SRE is disabled. Enabling the SRE it can track LTE-80MHz envelope with peak efficiency of 91%.
over 307V/us and bandwidth of over 275MHz for the linear amplifier. The slew-rate enhancement circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of out-
put without modifying the operating point of the remaining linear amplifier, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in 65nm CMOS process. The measurement results show the tracking of LTE-40MHz envelope with 93% peak efficiency at 1W output power, while the SRE is disabled. Enabling the SRE it can track LTE-80MHz envelope with peak efficiency of 91%.
ContributorsMahmoudidaryan, Parisa (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Mehdizad Taleie, Shahin (Committee member) / Arizona State University (Publisher)
Created2019
Description
This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below:
1) A transformer-based power combiner architecture for out-phasing transmitters
2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)
3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters
This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.
The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.
Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.
1) A transformer-based power combiner architecture for out-phasing transmitters
2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)
3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters
This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.
The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.
Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.
ContributorsMoallemi, Soroush (Author) / Kitchen, Jennifer (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2019
Description
Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.
ContributorsGrout, Kevin Samuel (Author) / Kitchen, Jennifer N (Thesis advisor) / Khalil, Waleed (Committee member) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Garrity, Douglas (Committee member) / Arizona State University (Publisher)
Created2019
Description
Polyurea is a highly versatile material used in coatings and armor systems to protect against extreme conditions such as ballistic impact, cavitation erosion, and blast loading. However, the relationships between microstructurally-dependent deformation mechanisms and the mechanical properties of polyurea are not yet fully understood, especially under extreme conditions. In this work, multi-scale coarse-grained models are developed to probe molecular dynamics across the wide range of time and length scales that these fundamental deformation mechanisms operate. In the first of these models, a high-resolution coarse-grained model of polyurea is developed, where similar to united-atom models, hydrogen atoms are modeled implicitly. This model was trained using a modified iterative Boltzmann inversion method that dramatically reduces the number of iterations required. Coarse-grained simulations using this model demonstrate that multiblock systems evolve to form a more interconnected hard phase, compared to the more interrupted hard phase composed of distinct ribbon-shaped domains found in diblock systems. Next, a reactive coarse-grained model is developed to simulate the influence of the difference in time scales for step-growth polymerization and phase segregation in polyurea. Analysis of the simulated cured polyurea systems reveals that more rapid reaction rates produce a smaller diameter ligaments in the gyroidal hard phase as well as increased covalent bonding connecting the hard domain ligaments as evidenced by a larger fraction of bridging segments and larger mean radius of gyration of the copolymer chains. The effect that these processing-induced structural variations have on the mechanical properties of the polymer was tested by simulating uniaxial compression, which revealed that the higher degree of hard domain connectivity leads to a 20% increase in the flow stress. A hierarchical multiresolution framework is proposed to fully link coarse-grained molecular simulations across a broader range of time scales, in which a family of coarse-grained models are developed. The models are connected using an incremental reverse–mapping scheme allowing for long time scale dynamics simulated at a highly coarsened resolution to be passed all the way to an atomistic representation.
ContributorsLiu, Minghao (Author) / Oswald, Jay (Thesis advisor) / Muhich, Christopher (Committee member) / Jiang, Hanqing (Committee member) / Peralta, Pedro (Committee member) / Jiao, Yang (Committee member) / Arizona State University (Publisher)
Created2020