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- Genre: Doctoral Dissertation
- Creators: Bakkaloglu, Bertan
- Creators: Papandreou-Suppappola, Antonia
- Member of: Theses and Dissertations
Description
Internet of Things (IoT) has become a popular topic in industry over the recent years, which describes an ecosystem of internet-connected devices or things that enrich the everyday life by improving our productivity and efficiency. The primary components of the IoT ecosystem are hardware, software and services. While the software and services of IoT system focus on data collection and processing to make decisions, the underlying hardware is responsible for sensing the information, preprocess and transmit it to the servers. Since the IoT ecosystem is still in infancy, there is a great need for rapid prototyping platforms that would help accelerate the hardware design process. However, depending on the target IoT application, different sensors are required to sense the signals such as heart-rate, temperature, pressure, acceleration, etc., and there is a great need for reconfigurable platforms that can prototype different sensor interfacing circuits.
This thesis primarily focuses on two important hardware aspects of an IoT system: (a) an FPAA based reconfigurable sensing front-end system and (b) an FPGA based reconfigurable processing system. To enable reconfiguration capability for any sensor type, Programmable ANalog Device Array (PANDA), a transistor-level analog reconfigurable platform is proposed. CAD tools required for implementation of front-end circuits on the platform are also developed. To demonstrate the capability of the platform on silicon, a small-scale array of 24×25 PANDA cells is fabricated in 65nm technology. Several analog circuit building blocks including amplifiers, bias circuits and filters are prototyped on the platform, which demonstrates the effectiveness of the platform for rapid prototyping IoT sensor interfaces.
IoT systems typically use machine learning algorithms that run on the servers to process the data in order to make decisions. Recently, embedded processors are being used to preprocess the data at the energy-constrained sensor node or at IoT gateway, which saves considerable energy for transmission and bandwidth. Using conventional CPU based systems for implementing the machine learning algorithms is not energy-efficient. Hence an FPGA based hardware accelerator is proposed and an optimization methodology is developed to maximize throughput of any convolutional neural network (CNN) based machine learning algorithm on a resource-constrained FPGA.
This thesis primarily focuses on two important hardware aspects of an IoT system: (a) an FPAA based reconfigurable sensing front-end system and (b) an FPGA based reconfigurable processing system. To enable reconfiguration capability for any sensor type, Programmable ANalog Device Array (PANDA), a transistor-level analog reconfigurable platform is proposed. CAD tools required for implementation of front-end circuits on the platform are also developed. To demonstrate the capability of the platform on silicon, a small-scale array of 24×25 PANDA cells is fabricated in 65nm technology. Several analog circuit building blocks including amplifiers, bias circuits and filters are prototyped on the platform, which demonstrates the effectiveness of the platform for rapid prototyping IoT sensor interfaces.
IoT systems typically use machine learning algorithms that run on the servers to process the data in order to make decisions. Recently, embedded processors are being used to preprocess the data at the energy-constrained sensor node or at IoT gateway, which saves considerable energy for transmission and bandwidth. Using conventional CPU based systems for implementing the machine learning algorithms is not energy-efficient. Hence an FPGA based hardware accelerator is proposed and an optimization methodology is developed to maximize throughput of any convolutional neural network (CNN) based machine learning algorithm on a resource-constrained FPGA.
ContributorsSuda, Naveen (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Yu, Shimeng (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2016
Description
Rail clamp circuits are widely used for electrostatic discharge (ESD) protection in semiconductor products today. A step-by-step design procedure for the traditional RC and single-inverter-based rail clamp circuit and the design, simulation, implementation, and operation of two novel rail clamp circuits are described for use in the ESD protection of complementary metal-oxide-semiconductor (CMOS) circuits. The step-by-step design procedure for the traditional circuit is technology-node independent, can be fully automated, and aims to achieve a minimal area design that meets specified leakage and ESD specifications under all valid process, voltage, and temperature (PVT) conditions. The first novel rail clamp circuit presented employs a comparator inside the traditional circuit to reduce the value of the time constant needed. The second circuit uses a dynamic time constant approach in which the value of the time constant is dynamically adjusted after the clamp is triggered. Important metrics for the two new circuits such as ESD performance, latch-on immunity, clamp recovery time, supply noise immunity, fastest power-on time supported, and area are evaluated over an industry-standard PVT space using SPICE simulations and measurements on a fabricated 40 nm test chip.
ContributorsVenkatasubramanian, Ramachandran (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2016
Description
The recent proposal of two-way relaying has attracted much attention due to its promising features for many practical scenarios. Hereby, two users communicate simultaneously in both directions to exchange their messages with the help of a relay node. This doctoral study investigates various aspects of two-way relaying. Specifically, the issue of asynchronism, lack of channel knowledge, transmission of correlated sources and multi-way relaying techniques involving multiple users are explored.
With the motivation of developing enabling techniques for two-way relay (TWR) channels experiencing excessive synchronization errors, two conceptually-different schemes are proposed to accommodate any relative misalignment between the signals received at any node. By designing a practical transmission/detection mechanism based on orthogonal frequency division multiplexing (OFDM), the proposed schemes perform significantly better than existing competing solutions. In a related direction, differential modulation is implemented for asynchronous TWR systems that lack the channel state information (CSI) knowledge. The challenge in this problem compared to the conventional point-to-point counterpart arises not only from the asynchrony but also from the existence of an interfering signal. Extensive numerical examples, supported by analytical work, are given to demonstrate the advantages of the proposed schemes.
Other important issues considered in this dissertation are related to the extension of the two-way relaying scheme to the multiple-user case, known as the multi-way relaying. First, a distributed source coding solution based on Slepian-Wolf coding is proposed to compress correlated messages close to the information theoretical limits in the context of multi-way relay (MWR) channels. Specifically, the syndrome approach based on low-density parity-check (LDPC) codes is implemented. A number of relaying strategies are considered for this problem offering a tradeoff between performance and complexity. The proposed solutions have shown significant improvements compared to the existing ones in terms of the achievable compression rates. On a different front, a novel approach to channel coding is proposed for the MWR channel based on the implementation of nested codes in a distributed manner. This approach ensures that each node decodes the messages of the other users without requiring complex operations at the relay, and at the same time, providing substantial benefits compared to the traditional routing solution.
With the motivation of developing enabling techniques for two-way relay (TWR) channels experiencing excessive synchronization errors, two conceptually-different schemes are proposed to accommodate any relative misalignment between the signals received at any node. By designing a practical transmission/detection mechanism based on orthogonal frequency division multiplexing (OFDM), the proposed schemes perform significantly better than existing competing solutions. In a related direction, differential modulation is implemented for asynchronous TWR systems that lack the channel state information (CSI) knowledge. The challenge in this problem compared to the conventional point-to-point counterpart arises not only from the asynchrony but also from the existence of an interfering signal. Extensive numerical examples, supported by analytical work, are given to demonstrate the advantages of the proposed schemes.
Other important issues considered in this dissertation are related to the extension of the two-way relaying scheme to the multiple-user case, known as the multi-way relaying. First, a distributed source coding solution based on Slepian-Wolf coding is proposed to compress correlated messages close to the information theoretical limits in the context of multi-way relay (MWR) channels. Specifically, the syndrome approach based on low-density parity-check (LDPC) codes is implemented. A number of relaying strategies are considered for this problem offering a tradeoff between performance and complexity. The proposed solutions have shown significant improvements compared to the existing ones in terms of the achievable compression rates. On a different front, a novel approach to channel coding is proposed for the MWR channel based on the implementation of nested codes in a distributed manner. This approach ensures that each node decodes the messages of the other users without requiring complex operations at the relay, and at the same time, providing substantial benefits compared to the traditional routing solution.
ContributorsSalīm, Aḥmad (Author) / Duman, Tolga M. (Thesis advisor) / Papandreou-Suppappola, Antonia (Committee member) / Tepedelenlioğlu, Cihan (Committee member) / Zhang, Junshan (Committee member) / Arizona State University (Publisher)
Created2015
Description
I propose a new communications scheme where signature signals are used to carry digital data by suitably modulating the signal parameters with information bits. One possible application for the proposed scheme is in underwater acoustic (UWA) communications; with this motivation, I demonstrate how it can be applied in UWA communications. In order to do that, I exploit existing parameterized models for mammalian sounds by using them as signature signals. Digital data is transmitted by mapping vectors of information bits to a carefully designed set of parameters with values obtained from the biomimetic signal models. To complete the overall system design, I develop appropriate receivers taking into account the specific UWA channel models. I present some numerical results from the analysis of data recorded during the Kauai Acomms MURI 2011 (KAM11) UWA communications experiment.
It is shown that the proposed communication scheme results in approximate channel models with amplitude-limited inputs and signal-dependent additive noise. Motivated by this observation, I study capacity of amplitude-limited channels under different transmission scenarios. Specifically, I consider fading channels, signal-dependent additive Gaussian noise channels, multiple-input multiple-output (MIMO) systems and parallel Gaussian channels under peak power constraints.
I also consider practical channel coding problems for channels with signal-dependent noise. I consider two specific models; signal-dependent additive Gaussian noise channels and Z-channels which serve as binary-input binary-output approximations to the Gaussian case. I propose a new upper bound on the probability of error, and utilize it for design of codes. I illustrate the tightness of the derived bounds and the performance of the designed codes via examples.
It is shown that the proposed communication scheme results in approximate channel models with amplitude-limited inputs and signal-dependent additive noise. Motivated by this observation, I study capacity of amplitude-limited channels under different transmission scenarios. Specifically, I consider fading channels, signal-dependent additive Gaussian noise channels, multiple-input multiple-output (MIMO) systems and parallel Gaussian channels under peak power constraints.
I also consider practical channel coding problems for channels with signal-dependent noise. I consider two specific models; signal-dependent additive Gaussian noise channels and Z-channels which serve as binary-input binary-output approximations to the Gaussian case. I propose a new upper bound on the probability of error, and utilize it for design of codes. I illustrate the tightness of the derived bounds and the performance of the designed codes via examples.
ContributorsElMoslimany, Ahmad (Author) / Duman, Tolga M. (Thesis advisor) / Papandreou-Suppappola, Antonia (Committee member) / Tepedelenlioğlu, Cihan (Committee member) / Kosut, Oliver (Committee member) / Arizona State University (Publisher)
Created2015
Description
A wideband hybrid envelope tracking modulator utilizing a hysteretic-controlled three-level switching converter and a slew-rate enhanced linear amplifierer is presented. In addition to smaller ripple and lower losses of three-level switching converters, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage VCF and eliminates conventional required calibration loop to control it. The hysteretic-controlled three-level switching converter provides a high percentage of power amplifier supply load current with lower ripple, reducing the linear amplifier high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the linear amplifier resulting in slew-rate of
over 307V/us and bandwidth of over 275MHz for the linear amplifier. The slew-rate enhancement circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of out-
put without modifying the operating point of the remaining linear amplifier, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in 65nm CMOS process. The measurement results show the tracking of LTE-40MHz envelope with 93% peak efficiency at 1W output power, while the SRE is disabled. Enabling the SRE it can track LTE-80MHz envelope with peak efficiency of 91%.
over 307V/us and bandwidth of over 275MHz for the linear amplifier. The slew-rate enhancement circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of out-
put without modifying the operating point of the remaining linear amplifier, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in 65nm CMOS process. The measurement results show the tracking of LTE-40MHz envelope with 93% peak efficiency at 1W output power, while the SRE is disabled. Enabling the SRE it can track LTE-80MHz envelope with peak efficiency of 91%.
ContributorsMahmoudidaryan, Parisa (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Mehdizad Taleie, Shahin (Committee member) / Arizona State University (Publisher)
Created2019
Description
Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required.
The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.
The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.
The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.
The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.
ContributorsSingh, Shrikant (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2019
Description
This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below:
1) A transformer-based power combiner architecture for out-phasing transmitters
2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)
3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters
This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.
The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.
Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.
1) A transformer-based power combiner architecture for out-phasing transmitters
2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)
3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters
This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.
The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.
Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.
ContributorsMoallemi, Soroush (Author) / Kitchen, Jennifer (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2019
Description
The marked increase in the inflow of remotely sensed data from satellites have trans- formed the Earth and Space Sciences to a data rich domain creating a rich repository for domain experts to analyze. These observations shed light on a diverse array of disciplines ranging from monitoring Earth system components to planetary explo- ration by highlighting the expected trend and patterns in the data. However, the complexity of these patterns from local to global scales, coupled with the volume of this ever-growing repository necessitates advanced techniques to sequentially process the datasets to determine the underlying trends. Such techniques essentially model the observations to learn characteristic parameters of data-generating processes and highlight anomalous planetary surface observations to help domain scientists for making informed decisions. The primary challenge in defining such models arises due to the spatio-temporal variability of these processes.
This dissertation introduces models of multispectral satellite observations that sequentially learn the expected trend from the data by extracting salient features of planetary surface observations. The main objectives are to learn the temporal variability for modeling dynamic processes and to build representations of features of interest that is learned over the lifespan of an instrument. The estimated model parameters are then exploited in detecting anomalies due to changes in land surface reflectance as well as novelties in planetary surface landforms. A model switching approach is proposed that allows the selection of the best matched representation given the observations that is designed to account for rate of time-variability in land surface. The estimated parameters are exploited to design a change detector, analyze the separability of change events, and form an expert-guided representation of planetary landforms for prioritizing the retrieval of scientifically relevant observations with both onboard and post-downlink applications.
This dissertation introduces models of multispectral satellite observations that sequentially learn the expected trend from the data by extracting salient features of planetary surface observations. The main objectives are to learn the temporal variability for modeling dynamic processes and to build representations of features of interest that is learned over the lifespan of an instrument. The estimated model parameters are then exploited in detecting anomalies due to changes in land surface reflectance as well as novelties in planetary surface landforms. A model switching approach is proposed that allows the selection of the best matched representation given the observations that is designed to account for rate of time-variability in land surface. The estimated parameters are exploited to design a change detector, analyze the separability of change events, and form an expert-guided representation of planetary landforms for prioritizing the retrieval of scientifically relevant observations with both onboard and post-downlink applications.
ContributorsChakraborty, Srija (Author) / Papandreou-Suppappola, Antonia (Thesis advisor) / Christensen, Philip R. (Philip Russel) (Thesis advisor) / Richmond, Christ (Committee member) / Maurer, Alexander (Committee member) / Arizona State University (Publisher)
Created2019
Description
Robotic lower limb prostheses provide new opportunities to help transfemoral amputees regain mobility. However, their application is impeded by that the impedance control parameters need to be tuned and optimized manually by prosthetists for each individual user in different task environments. Reinforcement learning (RL) is capable of automatically learning from interacting with the environment. It becomes a natural candidate to replace human prosthetists to customize the control parameters. However, neither traditional RL approaches nor the popular deep RL approaches are readily suitable for learning with limited number of samples and samples with large variations. This dissertation aims to explore new RL based adaptive solutions that are data-efficient for controlling robotic prostheses.
This dissertation begins by proposing a new flexible policy iteration (FPI) framework. To improve sample efficiency, FPI can utilize either on-policy or off-policy learning strategy, can learn from either online or offline data, and can even adopt exiting knowledge of an external critic. Approximate convergence to Bellman optimal solutions are guaranteed under mild conditions. Simulation studies validated that FPI was data efficient compared to several established RL methods. Furthermore, a simplified version of FPI was implemented to learn from offline data, and then the learned policy was successfully tested for tuning the control parameters online on a human subject.
Next, the dissertation discusses RL control with information transfer (RL-IT), or knowledge-guided RL (KG-RL), which is motivated to benefit from transferring knowledge acquired from one subject to another. To explore its feasibility, knowledge was extracted from data measurements of able-bodied (AB) subjects, and transferred to guide Q-learning control for an amputee in OpenSim simulations. This result again demonstrated that data and time efficiency were improved using previous knowledge.
While the present study is new and promising, there are still many open questions to be addressed in future research. To account for human adaption, the learning control objective function may be designed to incorporate human-prosthesis performance feedback such as symmetry, user comfort level and satisfaction, and user energy consumption. To make the RL based control parameter tuning practical in real life, it should be further developed and tested in different use environments, such as from level ground walking to stair ascending or descending, and from walking to running.
This dissertation begins by proposing a new flexible policy iteration (FPI) framework. To improve sample efficiency, FPI can utilize either on-policy or off-policy learning strategy, can learn from either online or offline data, and can even adopt exiting knowledge of an external critic. Approximate convergence to Bellman optimal solutions are guaranteed under mild conditions. Simulation studies validated that FPI was data efficient compared to several established RL methods. Furthermore, a simplified version of FPI was implemented to learn from offline data, and then the learned policy was successfully tested for tuning the control parameters online on a human subject.
Next, the dissertation discusses RL control with information transfer (RL-IT), or knowledge-guided RL (KG-RL), which is motivated to benefit from transferring knowledge acquired from one subject to another. To explore its feasibility, knowledge was extracted from data measurements of able-bodied (AB) subjects, and transferred to guide Q-learning control for an amputee in OpenSim simulations. This result again demonstrated that data and time efficiency were improved using previous knowledge.
While the present study is new and promising, there are still many open questions to be addressed in future research. To account for human adaption, the learning control objective function may be designed to incorporate human-prosthesis performance feedback such as symmetry, user comfort level and satisfaction, and user energy consumption. To make the RL based control parameter tuning practical in real life, it should be further developed and tested in different use environments, such as from level ground walking to stair ascending or descending, and from walking to running.
ContributorsGao, Xiang (Author) / Si, Jennie (Thesis advisor) / Huang, He Helen (Committee member) / Santello, Marco (Committee member) / Papandreou-Suppappola, Antonia (Committee member) / Arizona State University (Publisher)
Created2020
Description
A critical problem for airborne, ship board, and land based radars operating in maritime or littoral environments is the detection, identification and tracking of targets against backscattering caused by the roughness of the sea surface. Statistical models, such as the compound K-distribution (CKD), were shown to accurately describe two separate structures of the sea clutter intensity fluctuations. The first structure is the texture that is associated with long sea waves and exhibits long temporal decorrelation period. The second structure is the speckle that accounts for reflections from multiple scatters and exhibits a short temporal decorrelation period from pulse to pulse. Existing methods for estimating the CKD model parameters do not include the thermal noise power, which is critical for real sea clutter processing. Estimation methods that include the noise power are either computationally intensive or require very large data records.
This work proposes two new approaches for accurately estimating all three CKD model parameters, including noise power. The first method integrates, in an iterative fashion, the noise power estimation, using one-dimensional nonlinear curve fitting,
with the estimation of the shape and scale parameters, using closed-form solutions in terms of the CKD intensity moments. The second method is similar to the first except it replaces integer-based intensity moments with fractional moments which have been shown to achieve more accurate estimates of the shape parameter. These new methods can be implemented in real time without requiring large data records. They can also achieve accurate estimation performance as demonstrated with simulated and real sea clutter observation datasets. The work also investigates the numerically computed Cram\'er-Rao lower bound (CRLB) of the variance of the shape parameter estimate using intensity observations in thermal noise with unknown power. Using the CRLB, the asymptotic estimation performance behavior of the new estimators is studied and compared to that of other estimators.
This work proposes two new approaches for accurately estimating all three CKD model parameters, including noise power. The first method integrates, in an iterative fashion, the noise power estimation, using one-dimensional nonlinear curve fitting,
with the estimation of the shape and scale parameters, using closed-form solutions in terms of the CKD intensity moments. The second method is similar to the first except it replaces integer-based intensity moments with fractional moments which have been shown to achieve more accurate estimates of the shape parameter. These new methods can be implemented in real time without requiring large data records. They can also achieve accurate estimation performance as demonstrated with simulated and real sea clutter observation datasets. The work also investigates the numerically computed Cram\'er-Rao lower bound (CRLB) of the variance of the shape parameter estimate using intensity observations in thermal noise with unknown power. Using the CRLB, the asymptotic estimation performance behavior of the new estimators is studied and compared to that of other estimators.
ContributorsNorthrop, Judith (Author) / Papandreou-Suppappola, Antonia (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Tepedelenlioğlu, Cihan (Committee member) / Maurer, Alexander (Committee member) / Arizona State University (Publisher)
Created2019