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- Genre: Doctoral Dissertation
- Creators: Bakkaloglu, Bertan
- Creators: Gu, Bin
Description
When preparing for and responding to disasters, humanitarian organizations must run effective and efficient supply chains to deliver the resources needed by the affected population. The management of humanitarian supply chains include coordinating the flows of goods, finances, and information. This dissertation examines how humanitarian organizations can improve the distribution of information, which is critical for the planning and coordination of the other two flows. Specifically, I study the diffusion of information on social media platforms since such platforms have emerged as useful communication tools for humanitarian organizations during times of crisis.
In the first chapter, I identify several factors that affect how quickly information spreads on social media platforms. I utilized Twitter data from Hurricane Sandy, and the results indicate that the timing of information release and the influence of the content’s author determine information diffusion speed. The second chapter of this dissertation builds directly on the first study by also evaluating the rate at which social media content diffuses. A piece of content does not diffuse in isolation but, rather, coexists with other content on the same social media platform. After analyzing Twitter data from four distinct crises, the results indicate that other content’s diffusion often dampens a specific post’s diffusion speed. This is important for humanitarian organizations to recognize and carries implications for how they can coordinate with other organizations to avoid inhibiting the propagation of each other’s social media content. Finally, a user’s followers on social media platforms represent the user’s direct audience. The larger the user’s follower base, the more easily the same user can extensively broadcast information. Therefore, I study what drives the growth of humanitarian organizations’ follower bases during times of normalcy and emergency using Twitter data from one week before and one week after the 2016 Ecuador earthquake.
In the first chapter, I identify several factors that affect how quickly information spreads on social media platforms. I utilized Twitter data from Hurricane Sandy, and the results indicate that the timing of information release and the influence of the content’s author determine information diffusion speed. The second chapter of this dissertation builds directly on the first study by also evaluating the rate at which social media content diffuses. A piece of content does not diffuse in isolation but, rather, coexists with other content on the same social media platform. After analyzing Twitter data from four distinct crises, the results indicate that other content’s diffusion often dampens a specific post’s diffusion speed. This is important for humanitarian organizations to recognize and carries implications for how they can coordinate with other organizations to avoid inhibiting the propagation of each other’s social media content. Finally, a user’s followers on social media platforms represent the user’s direct audience. The larger the user’s follower base, the more easily the same user can extensively broadcast information. Therefore, I study what drives the growth of humanitarian organizations’ follower bases during times of normalcy and emergency using Twitter data from one week before and one week after the 2016 Ecuador earthquake.
ContributorsYoo, Eunae (Author) / Rabinovich, Elliot (Thesis advisor) / Gu, Bin (Thesis advisor) / Rand, William (Committee member) / Fowler, John (Committee member) / Arizona State University (Publisher)
Created2018
Description
Portable devices often require multiple power management IC (PMIC) to power different sub-modules, Li-ion batteries are well suited for portable devices because of its small size, high energy density and long life cycle. Since Li-ion battery is the major power source for portable device, fast and high-efficiency battery charging solution has become a major requirement in portable device application.
In the first part of dissertation, a high performance Li-ion switching battery charger is proposed. Cascaded two loop (CTL) control architecture is used for seamless CC-CV transition, time based technique is utilized to minimize controller area and power consumption. Time domain controller is implemented by using voltage controlled oscillator (VCO) and voltage controlled delay line (VCDL). Several efficiency improvement techniques such as segmented power-FET, quasi-zero voltage switching (QZVS) and switching frequency reduction are proposed. The proposed switching battery charger is able to provide maximum 2 A charging current and has an peak efficiency of 93.3%. By configure the charger as boost converter, the charger is able to provide maximum 1.5 A charging current while achieving 96.3% peak efficiency.
The second part of dissertation presents a digital low dropout regulator (DLDO) for system on a chip (SoC) in portable devices application. The proposed DLDO achieve fast transient settling time, lower undershoot/overshoot and higher PSR performance compared to state of the art. By having a good PSR performance, the proposed DLDO is able to power mixed signal load. To achieve a fast load transient response, a load transient detector (LTD) enables boost mode operation of the digital PI controller. The boost mode operation achieves sub microsecond settling time, and reduces the settling time by 50% to 250 ns, undershoot/overshoot by 35% to 250 mV and 17% to 125 mV without compromising the system stability.
In the first part of dissertation, a high performance Li-ion switching battery charger is proposed. Cascaded two loop (CTL) control architecture is used for seamless CC-CV transition, time based technique is utilized to minimize controller area and power consumption. Time domain controller is implemented by using voltage controlled oscillator (VCO) and voltage controlled delay line (VCDL). Several efficiency improvement techniques such as segmented power-FET, quasi-zero voltage switching (QZVS) and switching frequency reduction are proposed. The proposed switching battery charger is able to provide maximum 2 A charging current and has an peak efficiency of 93.3%. By configure the charger as boost converter, the charger is able to provide maximum 1.5 A charging current while achieving 96.3% peak efficiency.
The second part of dissertation presents a digital low dropout regulator (DLDO) for system on a chip (SoC) in portable devices application. The proposed DLDO achieve fast transient settling time, lower undershoot/overshoot and higher PSR performance compared to state of the art. By having a good PSR performance, the proposed DLDO is able to power mixed signal load. To achieve a fast load transient response, a load transient detector (LTD) enables boost mode operation of the digital PI controller. The boost mode operation achieves sub microsecond settling time, and reduces the settling time by 50% to 250 ns, undershoot/overshoot by 35% to 250 mV and 17% to 125 mV without compromising the system stability.
ContributorsLim, Chai Yong (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ogras, Umit Y. (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2018
Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
In this dissertation a new wideband circular HIS is proposed. The circular periodicity made it possible to illuminate the surface with a cylindrical TEMz wave and; a novel technique is utilized to make it wideband. Two models are developed to analyze the
reflection characteristics of the proposed HIS.
The circularly symmetric high impedance surface is used as a ground plane for the design of a low-profile loop and spiral radiating elements. It is shown that a HIS with circular periodicity provides a wider operational bandwidth for curvilinear radiating elements such, such as loops and spirals, compared to canonical rectangular HISs.
It is also observed that, with the aid of a circular HIS ground plane the gain of a loop and a spiral increases compared to when a perfect magnetic conductor (PMC) or rectangular HIS is used as a ground plane. The circular HIS was fabricated and the loop and spiral elements were placed individually in close proximity to it.
Also, due to the growing demand for low-radar signature (RCS) antennas for advanced airborne vehicles, curved and flexible HIS ground planes, which meet both the aerodynamic and low RCS requirements, have recently become popular candidates within the antenna and microwave technology. This encouraged us, to propose a spherical HIS where a 2-D curvature is introduced to the previously designed flat HIS.
The major problem associated with spherical HIS is the impact of the curvature on its reflection properties. After characterization of the flat circular HIS, which is addressed in the first part of this dissertation, a spherical curvature is introduced to the flat circular HIS and its impact on the reflection properties was examined when it was illuminated with the same cylindrical TEMz wave. The same technique, as for the flat HIS ground plane, is utilized to make the spherical HIS wideband. A loop and spiral element were placed in the vicinity of the curved HIS and their performanceswere investigated. The HISs were also fabricated and measurements were conducted to verify the simulations. An excellent agreement was observed.
reflection characteristics of the proposed HIS.
The circularly symmetric high impedance surface is used as a ground plane for the design of a low-profile loop and spiral radiating elements. It is shown that a HIS with circular periodicity provides a wider operational bandwidth for curvilinear radiating elements such, such as loops and spirals, compared to canonical rectangular HISs.
It is also observed that, with the aid of a circular HIS ground plane the gain of a loop and a spiral increases compared to when a perfect magnetic conductor (PMC) or rectangular HIS is used as a ground plane. The circular HIS was fabricated and the loop and spiral elements were placed individually in close proximity to it.
Also, due to the growing demand for low-radar signature (RCS) antennas for advanced airborne vehicles, curved and flexible HIS ground planes, which meet both the aerodynamic and low RCS requirements, have recently become popular candidates within the antenna and microwave technology. This encouraged us, to propose a spherical HIS where a 2-D curvature is introduced to the previously designed flat HIS.
The major problem associated with spherical HIS is the impact of the curvature on its reflection properties. After characterization of the flat circular HIS, which is addressed in the first part of this dissertation, a spherical curvature is introduced to the flat circular HIS and its impact on the reflection properties was examined when it was illuminated with the same cylindrical TEMz wave. The same technique, as for the flat HIS ground plane, is utilized to make the spherical HIS wideband. A loop and spiral element were placed in the vicinity of the curved HIS and their performanceswere investigated. The HISs were also fabricated and measurements were conducted to verify the simulations. An excellent agreement was observed.
ContributorsAmiri, Mikal Askarian (Author) / Balanis, Constantine A (Thesis advisor) / Aberle, James T (Committee member) / Bakkaloglu, Bertan (Committee member) / Trichopoulos, Georgios C (Committee member) / Arizona State University (Publisher)
Created2018
Description
The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator.
Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2.
Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2.
ContributorsMagod Ramakrishna, Raveesh (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Kitchen, Jennifer (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2018
Description
As integrated technologies are scaling down, there is an increasing trend in the
process,voltage and temperature (PVT) variations of highly integrated RF systems.
Accounting for these variations during the design phase requires tremendous amount
of time for prediction of RF performance and optimizing it accordingly. Thus, there
is an increasing gap between the need to relax the RF performance requirements at
the design phase for rapid development and the need to provide high performance
and low cost RF circuits that function with PVT variations. No matter how care-
fully designed, RF integrated circuits (ICs) manufactured with advanced technology
nodes necessitate lengthy post-production calibration and test cycles with expensive
RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast
measurement of performance parameters during both post-production and in-eld op-
eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip
measurement of RF performance parameters. In this dissertation, three aspects of
automated test and calibration, including DFT mathematical model, BIST hardware
and built-in calibration are covered for RF front-end blocks.
First, the theoretical foundation of a post-production test of RF integrated phased
array antennas is proposed by developing the mathematical model to measure gain
and phase mismatches between antenna elements without any electrical contact. The
proposed technique is fast, cost-efficient and uses near-field measurement of radiated
power from antennas hence, it requires single test setup, it has easy implementation
and it is short in time which makes it viable for industrialized high volume integrated
IC production test.
Second, a BIST model intended for the characterization of I/Q offset, gain and
phase mismatch of IQ transmitters without relying on external equipment is intro-
duced. The proposed BIST method is based on on-chip amplitude measurement as
in prior works however,here the variations in the BIST circuit do not affect the target
parameter estimation accuracy since measurements are designed to be relative. The
BIST circuit is implemented in 130nm technology and can be used for post-production
and in-field calibration.
Third, a programmable low noise amplifier (LNA) is proposed which is adaptable
to different application scenarios depending on the specification requirements. Its
performance is optimized with regards to required specifications e.g. distance, power
consumption, BER, data rate, etc.The statistical modeling is used to capture the
correlations among measured performance parameters and calibration modes for fast
adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by
embedding built-in tuning knobs in LNA design in 130nm technology. The tuning
knobs are carefully designed to provide independent combinations of important per-
formance parameters such as gain and linearity. Minimum number of switches are
used to provide the desired tuning range without a need for an external analog input.
process,voltage and temperature (PVT) variations of highly integrated RF systems.
Accounting for these variations during the design phase requires tremendous amount
of time for prediction of RF performance and optimizing it accordingly. Thus, there
is an increasing gap between the need to relax the RF performance requirements at
the design phase for rapid development and the need to provide high performance
and low cost RF circuits that function with PVT variations. No matter how care-
fully designed, RF integrated circuits (ICs) manufactured with advanced technology
nodes necessitate lengthy post-production calibration and test cycles with expensive
RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast
measurement of performance parameters during both post-production and in-eld op-
eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip
measurement of RF performance parameters. In this dissertation, three aspects of
automated test and calibration, including DFT mathematical model, BIST hardware
and built-in calibration are covered for RF front-end blocks.
First, the theoretical foundation of a post-production test of RF integrated phased
array antennas is proposed by developing the mathematical model to measure gain
and phase mismatches between antenna elements without any electrical contact. The
proposed technique is fast, cost-efficient and uses near-field measurement of radiated
power from antennas hence, it requires single test setup, it has easy implementation
and it is short in time which makes it viable for industrialized high volume integrated
IC production test.
Second, a BIST model intended for the characterization of I/Q offset, gain and
phase mismatch of IQ transmitters without relying on external equipment is intro-
duced. The proposed BIST method is based on on-chip amplitude measurement as
in prior works however,here the variations in the BIST circuit do not affect the target
parameter estimation accuracy since measurements are designed to be relative. The
BIST circuit is implemented in 130nm technology and can be used for post-production
and in-field calibration.
Third, a programmable low noise amplifier (LNA) is proposed which is adaptable
to different application scenarios depending on the specification requirements. Its
performance is optimized with regards to required specifications e.g. distance, power
consumption, BER, data rate, etc.The statistical modeling is used to capture the
correlations among measured performance parameters and calibration modes for fast
adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by
embedding built-in tuning knobs in LNA design in 130nm technology. The tuning
knobs are carefully designed to provide independent combinations of important per-
formance parameters such as gain and linearity. Minimum number of switches are
used to provide the desired tuning range without a need for an external analog input.
ContributorsShafiee, Maryam (Author) / Ozev, Sule (Thesis advisor) / Diaz, Rodolfo (Committee member) / Ogras, Umit Y. (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2018
Description
There is an increasing demand for fully integrated point-of-load (POL) isolated DC-DC converters that can provide an isolation barrier between the primary and the secondary side, while delivering a low ripple, low noise regulated voltage at their isolated sides to a high dynamic range, sensitive mixed signal devices, such as sensors, current-shunt-monitors and ADCs. For these applications, smaller system size and integration level is important because the whole system may need to fit to limited space. Traditional methods for providing isolated power are discrete solutions using bulky transformers. Miniaturization of isolated POL regulators is becoming highly desirable for low power applications.
A fully integrated, low noise isolated point-of-load DC-DC converter for supply regulation of high dynamic range analog and mixed signal sensor signal-chains is presented. The isolated DC-DC converter utilizes an integrated planar air-core micro-transformer as a coupled resonator and isolation barrier and enables direct connection of low-voltage mixed signal circuits to higher supply rails. The air core transformer is driven at its primary resonant frequency of 100 MHz to achieve maximum power transfer. A mixed-signal perturb-and-observe based frequency search algorithm is developed to improve maximum power transfer efficiency by 60% across the isolation barrier compared to fixed driving frequency method. The isolated converter’s output ripple is reduced by utilizing spread spectrum clocking in the driver. An isolated PMOS LDO in the secondary side is used to suppress switching noise and ripple by 21dB. Conducted and radiated EMI distribution on the IC is measured by a set of integrated ring oscillator based noise sensors with -68dBm noise sensitivity. The proposed isolated converter achieves highest level of integration with respect to earlier reported integrated isolated converters, while providing 50V on-chip junction isolation without the need for extra silicon post-processing steps.
A fully integrated, low noise isolated point-of-load DC-DC converter for supply regulation of high dynamic range analog and mixed signal sensor signal-chains is presented. The isolated DC-DC converter utilizes an integrated planar air-core micro-transformer as a coupled resonator and isolation barrier and enables direct connection of low-voltage mixed signal circuits to higher supply rails. The air core transformer is driven at its primary resonant frequency of 100 MHz to achieve maximum power transfer. A mixed-signal perturb-and-observe based frequency search algorithm is developed to improve maximum power transfer efficiency by 60% across the isolation barrier compared to fixed driving frequency method. The isolated converter’s output ripple is reduced by utilizing spread spectrum clocking in the driver. An isolated PMOS LDO in the secondary side is used to suppress switching noise and ripple by 21dB. Conducted and radiated EMI distribution on the IC is measured by a set of integrated ring oscillator based noise sensors with -68dBm noise sensitivity. The proposed isolated converter achieves highest level of integration with respect to earlier reported integrated isolated converters, while providing 50V on-chip junction isolation without the need for extra silicon post-processing steps.
ContributorsLiu, Chengxi (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Song, Hongjiang (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
Online product ratings offer consumers information about products. In this dissertation, I explore how the design of the rating system impacts consumers’ sharing behavior and how different players are affected by rating mechanisms. The first two chapters investigate how consumers choose to share their experiences of different attributes, how their preferences are reflected in numerical ratings and textual reviews, whether and how multi-dimensional rating systems affect consumer satisfaction through product ratings, and whether and how multi-dimensional rating systems affect the interplay between numerical ratings and textual reviews. The identification strategy of the observational study hinges on a natural experiment on TripAdvisor when the website reengineered its rating system from single-dimensional to multi-dimensional in January 2009. Rating data on the same set of restaurants from Yelp, were used to identify the causal effect using a difference-in-difference approach. Text mining skills were deployed to identify potential topics from textual reviews when consumers didn’t provide dimensional ratings in both SD and MD systems. Results show that ratings in a single-dimensional rating system have a downward trend and a higher dispersion, whereas ratings in a multi-dimensional rating system are significantly higher and convergent. Textual reviews in MDR are in greater width and depth than textual reviews in SDR. The third chapter tries to uncover how the introduction of monetary incentives would influence different players in the online e-commerce market in the short term and in the long run. These three studies together contribute to the understanding of rating system/mechanism designs and different players in the online market.
ContributorsLiu, Ying (Author) / Chen, Pei-Yu (Thesis advisor) / Hong, Yili (Thesis advisor) / Gu, Bin (Committee member) / Arizona State University (Publisher)
Created2018
Description
The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power ratio (PAPR) even after applying crest factor reduction. Being the most power-hungry component in the radio frequency (RF) transmitter, power amplifiers (PA) for infrastructure applications, need to operate efficiently at the presence of these high PAPR signals while maintaining reasonable linearity performance which could be improved by moderate digital pre-distortion (DPD) techniques. This strict requirement of operating efficiently at average power level while being capable of delivering the peak power, made the load modulated PAs such as Doherty PA, Outphasing PA, various Envelope Tracking PAs, Polar transmitters and most recently the load modulated balanced PA, the prime candidates for such application. However, due to its simpler architecture and ability to deliver RF power efficiently with good linearity performance has made Doherty PA (DPA) the most popular solution and has been deployed almost exclusively for wireless infrastructure application all over the world.
Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels.
Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels.
ContributorsRuhul Hasin, Muhammad (Author) / Kitchen, Jennifer (Thesis advisor) / Aberle, James T., 1961- (Committee member) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2018
Description
Fraud is defined as the utilization of deception for illegal gain by hiding the true nature of the activity. While organizations lose around $3.7 trillion in revenue due to financial crimes and fraud worldwide, they can affect all levels of society significantly. In this dissertation, I focus on credit card fraud in online transactions. Every online transaction comes with a fraud risk and it is the merchant's liability to detect and stop fraudulent transactions. Merchants utilize various mechanisms to prevent and manage fraud such as automated fraud detection systems and manual transaction reviews by expert fraud analysts. Many proposed solutions mostly focus on fraud detection accuracy and ignore financial considerations. Also, the highly effective manual review process is overlooked. First, I propose Profit Optimizing Neural Risk Manager (PONRM), a selective classifier that (a) constitutes optimal collaboration between machine learning models and human expertise under industrial constraints, (b) is cost and profit sensitive. I suggest directions on how to characterize fraudulent behavior and assess the risk of a transaction. I show that my framework outperforms cost-sensitive and cost-insensitive baselines on three real-world merchant datasets. While PONRM is able to work with many supervised learners and obtain convincing results, utilizing probability outputs directly from the trained model itself can pose problems, especially in deep learning as softmax output is not a true uncertainty measure. This phenomenon, and the wide and rapid adoption of deep learning by practitioners brought unintended consequences in many situations such as in the infamous case of Google Photos' racist image recognition algorithm; thus, necessitated the utilization of the quantified uncertainty for each prediction. There have been recent efforts towards quantifying uncertainty in conventional deep learning methods (e.g., dropout as Bayesian approximation); however, their optimal use in decision making is often overlooked and understudied. Thus, I present a mixed-integer programming framework for selective classification called MIPSC, that investigates and combines model uncertainty and predictive mean to identify optimal classification and rejection regions. I also extend this framework to cost-sensitive settings (MIPCSC) and focus on the critical real-world problem, online fraud management and show that my approach outperforms industry standard methods significantly for online fraud management in real-world settings.
ContributorsYildirim, Mehmet Yigit (Author) / Davulcu, Hasan (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Huang, Dijiang (Committee member) / Hsiao, Ihan (Committee member) / Arizona State University (Publisher)
Created2019