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- Genre: Academic theses
- Creators: Bakkaloglu, Bertan
- Creators: Vittal, Vijay
- Status: Published
Description
With the increased penetration of solar PV, it has become considerable for the system planners and operators to recognize the impact of PV plant on the power system stability and reliable operation of grid. This enforced the development of adequate PV system models for grid planning and interconnection studies. Western Electricity Coordinating Council (WECC) Renewable Energy Modeling Task Force has developed generator/converter, electrical controller and plant controller modules to represent positive sequence solar PV plant model for grid interconnection studies. This work performs the validation of these PV plant models against the field measured data. Sheer purpose of this validation effort is to authenticate model accuracy and their capability to represent dynamics of a solar PV plant. Both steady state and dynamic models of PV plant are discussed in this work. An algorithm to fine tune and determine the electrical controller and plant controller module gains is developed. Controller gains as obtained from proposed algorithm is used in PV plant dynamic simulation model. Model is simulated for a capacitor bank switching event and simulated plant response is then compared with field measured data. Validation results demonstrate that, the proposed algorithm is performing well to determine controller gains within the region of interest. Also, it concluded that developed PV plant models are adequate enough to capture PV plant dynamics.
ContributorsSoni, Sachin (Author) / Karady, George G. (Thesis advisor) / Undrill, John (Committee member) / Vittal, Vijay (Committee member) / Arizona State University (Publisher)
Created2014
Description
To uncover the neural correlates to go-directed behavior, single unit action potentials are considered fundamental computing units and have been examined by different analytical methodologies under a broad set of hypotheses. Using a behaving rat performing a directional choice learning task, we aim to study changes in rat's cortical neural patterns while he improved his task performance accuracy from chance to 80% or higher. Specifically, simultaneous multi-channel single unit neural recordings from the rat's agranular medial (AGm) and Agranular lateral (AGl) cortices were analyzed using joint peristimulus time histogram (JPSTHs), which effectively unveils firing coincidences in neural action potentials. My results based on data from six rats revealed that coincidences of pair-wise neural action potentials are higher when rats were performing the task than they were not at the learning stage, and this trend abated after the rats learned the task. Another finding is that the coincidences at the learning stage are stronger than that when the rats learned the task especially when they were performing the task. Therefore, this coincidence measure is the highest when the rats were performing the task at the learning stage. This may suggest that neural coincidences play a role in the coordination and communication among populations of neurons engaged in a purposeful act. Additionally, attention and working memory may have contributed to the modulation of neural coincidences during the designed task.
ContributorsCheng, Bing (Author) / Si, Jennie (Thesis advisor) / Chae, Junseok (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2014
Description
With growing complexity of power grid interconnections, power systems may become increasingly vulnerable to low frequency oscillations (especially inter-area oscillations) and dependent on stabilizing controls using either local signals or wide-area signals to provide adequate damping. In recent years, the ability and potential to use wide-area signals for control purposes has increased since a significant investment has been made in the U. S. in deploying synchrophasor measurement technology. Fast and reliable communication systems are essential to enable the use of wide-area signals in controls. If wide-area signals find increased applicability in controls the security and reliability of power systems could be vulnerable to disruptions in communication systems. Even though numerous modern techniques have been developed to lower the probability of communication errors, communication networks cannot be designed to be always reliable. Given this background the motivation of this work is to build resiliency in the power grid controls to respond to failures in the communication network when wide-area control signals are used. In addition, this work also deals with the delay uncertainty associated with the wide-area signal transmission. In order to counteract the negative impact of communication failures on control effectiveness, two approaches are proposed and both approaches are motivated by considering the use of a robustly designed supplementary damping control (SDC) framework associated with a static VAr compensator (SVC). When there is no communication failure, the designed controller guarantees enhanced improvement in damping performance. When the wide-area signal in use is lost due to a communication failure, however, the resilient control provides the required damping of the inter-area oscillations by either utilizing another wide-area measurement through a healthy communication route or by simply utilizing an appropriate local control signal. Simulation results prove that with either of the proposed controls included, the system is stabilized regardless of communication failures, and thereby the reliability and sustainability of power systems is improved. The proposed approaches can be extended without loss of generality to the design of any resilient controller in cyber-physical engineering systems.
ContributorsZhang, Song (Author) / Vittal, Vijay (Thesis advisor) / Heydt, Gerald (Committee member) / Si, Jennie (Committee member) / Undrill, John (Committee member) / Arizona State University (Publisher)
Created2014
Description
Isolated DC/DC converters are used to provide electrical isolation between two supply domain systems. A fully integrated isolated DC/DC converter having no board-level components and fabricated using standard integrated circuits (IC) process is highly desirable in order to increase the system reliability and reduce costs. The isolation between the low-voltage side and high-voltage side of the converter is realized by a transformer that transfers energy while blocking the DC loop. The resonant mode power oscillator is used to enable high efficiency power transfer. The on-chip transformer is expected to have high coil inductance, high quality factors and high coupling coefficient to reduce the loss in the oscillation. The performance of a transformer is highly dependent on the vertical structure, horizontal geometry and other indispensable structures that make it compatible with the IC process such as metal fills and patterned ground shield (PGS). With the help of three-dimensional (3-D) electro-magnetic (EM) simulation software, the 3-D transformer model is simulated and the simulation result is got with high accuracy.
In this thesis an on-chip transformer for a fully integrated DC/DC converter using standard IC process is developed. Different types of transformers are modeled and simulated in HFSS. The performances are compared to select the optimum design. The effects of the additional structures including PGS and metal fills are also simulated. The transformer is tested with a network analyzer and the testing results show a good consistency with the simulation results when taking the chip traces, printed circuit board (PCB) traces, bond wires and SMA connectors into account.
In this thesis an on-chip transformer for a fully integrated DC/DC converter using standard IC process is developed. Different types of transformers are modeled and simulated in HFSS. The performances are compared to select the optimum design. The effects of the additional structures including PGS and metal fills are also simulated. The transformer is tested with a network analyzer and the testing results show a good consistency with the simulation results when taking the chip traces, printed circuit board (PCB) traces, bond wires and SMA connectors into account.
ContributorsZhao, Yao (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
Photovoltaic (PV) systems are affected by converter losses, partial shading and other mismatches in the panels. This dissertation introduces a sub-panel maximum power point tracking (MPPT) architecture together with an integrated CMOS current sensor circuit on a chip to reduce the mismatch effects, losses and increase the efficiency of the PV system. The sub-panel MPPT increases the efficiency of the PV during the shading and replaces the bypass diodes in the panels with an integrated MPPT and DC-DC regulator. For the integrated MPPT and regulator, the research developed an integrated standard CMOS low power and high common mode range Current-to-Digital Converter (IDC) circuit and its application for DC-DC regulator and MPPT. The proposed charge based CMOS switched-capacitor circuit directly digitizes the output current of the DC-DC regulator without an analog-to-digital converter (ADC) and the need for high-voltage process technology. Compared to the resistor based current-sensing methods that requires current-to-voltage circuit, gain block and ADC, the proposed CMOS IDC is a low-power efficient integrated circuit that achieves high resolution, lower complexity, and lower power consumption. The IDC circuit is fabricated on a 0.7 um CMOS process, occupies 2mm x 2mm and consumes less than 27mW. The IDC circuit has been tested and used for boost DC-DC regulator and MPPT for photo-voltaic system. The DC-DC converter has an efficiency of 95%. The sub-module level power optimization improves the output power of a shaded panel by up to 20%, compared to panel MPPT with bypass diodes.
ContributorsMarti-Arbona, Edgar (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2014
Description
Modern day deep sub-micron SOC architectures often demand very low supply noise levels. As supply voltage decreases with decreasing deep sub-micron gate length, noise on the power supply starts playing a dominant role in noise-sensitive analog blocks, especially high precision ADC, PLL, and RF SOC's. Most handheld and portable applications and highly sensitive medical instrumentation circuits tend to use low noise regulators as on-chip or on board power supply. Nonlinearities associated with LNA's, mixers and oscillators up-convert low frequency noise with the signal band. Specifically, synthesizer and TCXO phase noise, LNA and mixer noise figure, and adjacent channel power ratios of the PA are heavily influenced by the supply noise and ripple. This poses a stringent requirement on a very low noise power supply with high accuracy and fast transient response. Low Dropout (LDO) regulators are preferred over switching regulators for these applications due to their attractive low noise and low ripple features. LDO's shield sensitive blocks from high frequency fluctuations on the power supply while providing high accuracy, fast response supply regulation.
This research focuses on developing innovative techniques to reduce the noise of any generic wideband LDO, stable with or without load capacitor. The proposed techniques include Switched RC Filtering to reduce the Bandgap Reference noise, Current Mode Chopping to reduce the Error Amplifier noise & MOS-R based RC filter to reduce the noise due to bias current. The residual chopping ripple was reduced using a Switched Capacitor notch filter. Using these techniques, the integrated noise of a wideband LDO was brought down to 15µV in the integration band of 10Hz to 100kHz. These techniques can be integrated into any generic LDO without any significant area overhead.
This research focuses on developing innovative techniques to reduce the noise of any generic wideband LDO, stable with or without load capacitor. The proposed techniques include Switched RC Filtering to reduce the Bandgap Reference noise, Current Mode Chopping to reduce the Error Amplifier noise & MOS-R based RC filter to reduce the noise due to bias current. The residual chopping ripple was reduced using a Switched Capacitor notch filter. Using these techniques, the integrated noise of a wideband LDO was brought down to 15µV in the integration band of 10Hz to 100kHz. These techniques can be integrated into any generic LDO without any significant area overhead.
ContributorsMagod Ramakrishna, Raveesh (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
An important operating aspect of all transmission systems is power system stability
and satisfactory dynamic performance. The integration of renewable resources in general, and photovoltaic resources in particular into the grid has created new engineering issues. A particularly problematic operating scenario occurs when conventional generation is operated at a low level but photovoltaic solar generation is at a high level. Significant solar photovoltaic penetration as a renewable resource is becoming a reality in some electric power systems. In this thesis, special attention is given to photovoltaic generation in an actual electric power system: increased solar penetration has resulted in significant strides towards meeting renewable portfolio standards. The impact of solar generation integration on power system dynamics is studied and evaluated.
This thesis presents the impact of high solar penetration resulting in potentially
problematic low system damping operating conditions. This is the case because the power system damping provided by conventional generation may be insufficient due to reduced system inertia and change in power flow patterns affecting synchronizing and damping capability in the AC system. This typically occurs because conventional generators are rescheduled or shut down to allow for the increased solar production. This problematic case may occur at any time of the year but during the springtime months of March-May, when the system load is low and the ambient temperature is relatively low, there is the potential that over voltages may occur in the high voltage transmission system. Also, reduced damping in system response to disturbances may occur. An actual case study is considered in which real operating system data are used. Solutions to low damping cases are discussed and a solution based on the retuning of a conventional power system stabilizer is given in the thesis.
and satisfactory dynamic performance. The integration of renewable resources in general, and photovoltaic resources in particular into the grid has created new engineering issues. A particularly problematic operating scenario occurs when conventional generation is operated at a low level but photovoltaic solar generation is at a high level. Significant solar photovoltaic penetration as a renewable resource is becoming a reality in some electric power systems. In this thesis, special attention is given to photovoltaic generation in an actual electric power system: increased solar penetration has resulted in significant strides towards meeting renewable portfolio standards. The impact of solar generation integration on power system dynamics is studied and evaluated.
This thesis presents the impact of high solar penetration resulting in potentially
problematic low system damping operating conditions. This is the case because the power system damping provided by conventional generation may be insufficient due to reduced system inertia and change in power flow patterns affecting synchronizing and damping capability in the AC system. This typically occurs because conventional generators are rescheduled or shut down to allow for the increased solar production. This problematic case may occur at any time of the year but during the springtime months of March-May, when the system load is low and the ambient temperature is relatively low, there is the potential that over voltages may occur in the high voltage transmission system. Also, reduced damping in system response to disturbances may occur. An actual case study is considered in which real operating system data are used. Solutions to low damping cases are discussed and a solution based on the retuning of a conventional power system stabilizer is given in the thesis.
ContributorsPethe, Anushree Sanjeev (Author) / Vittal, Vijay (Thesis advisor) / Heydt, Gerald T (Thesis advisor) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2015
Description
An increase in the number of inverter-interfaced photovoltaic (PV) generators on existing distribution feeders affects the design, operation, and control of the distri- bution systems. Existing distribution system analysis tools are capable of supporting only snapshot and quasi-static analyses. Capturing the dynamic effects of the PV generators during the variation in the distribution system states is necessary when studying the effects of controller bandwidths, multiple voltage correction devices, and anti-islanding. This work explores the use of dynamic phasors and differential algebraic equations (DAE) for impact analysis of the PV generators on the existing distribution feeders.
The voltage unbalance induced by PV generators can aggravate the existing unbalance due to load mismatch. An increased phase unbalance significantly adds to the neutral currents, excessive neutral to ground voltages and violate the standards for unbalance factor. The objective of this study is to analyze and quantify the impacts of unbalanced PV installations on a distribution feeder. Additionally, a power electronic converter solution is proposed to mitigate the identified impacts and validate the solution's effectiveness through detailed simulations in OpenDSS.
The benefits associated with the use of energy storage systems for electric- utility-related applications are also studied. This research provides a generalized framework for strategic deployment of a lithium-ion based energy storage system to increase their benefits in a distribution feeder. A significant amount of work has been performed for a detailed characterization of the life cycle costs of an energy storage system. The objectives include - reduction of the substation transformer losses, reduction of the life cycle cost for an energy storage system, and accommodate the PV variability.
The distribution feeder laterals in the distribution feeder with relatively high PV generation as compared to the load can be operated as microgrids to achieve reliability, power quality and economic benefits. However, the renewable resources are intermittent and stochastic in nature. A novel approach for sizing and scheduling the energy storage system and microtrubine is proposed for reliable operation of microgrids. The size and schedule of the energy storage system and microturbine are determined using Benders' decomposition, considering the PV generation as a stochastic resource.
The voltage unbalance induced by PV generators can aggravate the existing unbalance due to load mismatch. An increased phase unbalance significantly adds to the neutral currents, excessive neutral to ground voltages and violate the standards for unbalance factor. The objective of this study is to analyze and quantify the impacts of unbalanced PV installations on a distribution feeder. Additionally, a power electronic converter solution is proposed to mitigate the identified impacts and validate the solution's effectiveness through detailed simulations in OpenDSS.
The benefits associated with the use of energy storage systems for electric- utility-related applications are also studied. This research provides a generalized framework for strategic deployment of a lithium-ion based energy storage system to increase their benefits in a distribution feeder. A significant amount of work has been performed for a detailed characterization of the life cycle costs of an energy storage system. The objectives include - reduction of the substation transformer losses, reduction of the life cycle cost for an energy storage system, and accommodate the PV variability.
The distribution feeder laterals in the distribution feeder with relatively high PV generation as compared to the load can be operated as microgrids to achieve reliability, power quality and economic benefits. However, the renewable resources are intermittent and stochastic in nature. A novel approach for sizing and scheduling the energy storage system and microtrubine is proposed for reliable operation of microgrids. The size and schedule of the energy storage system and microturbine are determined using Benders' decomposition, considering the PV generation as a stochastic resource.
ContributorsNagarajan, Adarsh (Author) / Ayyanar, Raja (Thesis advisor) / Vittal, Vijay (Committee member) / Heydt, Gerald (Committee member) / Karady, George G. (Committee member) / Arizona State University (Publisher)
Created2015
Description
The aging process due to Bias Temperature Instability (both NBTI and PBTI) and Channel Hot Carrier (CHC) is a key limiting factor of circuit lifetime in CMOS design. Threshold voltage shift due to BTI is a strong function of stress voltage and temperature complicating stress and recovery prediction. This poses a unique challenge for long-term aging prediction for wide range of stress patterns. Traditional approaches usually resort to an average stress waveform to simplify the lifetime prediction. They are efficient, but fail to capture circuit operation, especially under dynamic voltage scaling (DVS) or in analog/mixed signal designs where the stress waveform is much more random. This work presents a suite of modelling solutions for BTI that enable aging simulation under all possible stress conditions. Key features of this work are compact models to predict BTI aging based on Reaction-Diffusion theory when the stress voltage is varying. The results to both reaction-diffusion (RD) and trapping-detrapping (TD) mechanisms are presented to cover underlying physics. Silicon validation of these models is performed at 28nm, 45nm and 65nm technology nodes, at both device and circuit levels. Efficient simulation leveraging the BTI models under DVS and random input waveform is applied to both digital and analog representative circuits such as ring oscillators and LNA. Both physical mechanisms are combined into a unified model which improves prediction accuracy at 45nm and 65nm nodes. Critical failure condition is also illustrated based on NBTI and PBTI at 28nm. A comprehensive picture for duty cycle shift is shown. DC stress under clock gating schemes results in monotonic shift in duty cycle which an AC stress causes duty cycle to converge close to 50% value. Proposed work provides a general and comprehensive solution to aging analysis under random stress patterns under BTI.
Channel hot carrier (CHC) is another dominant degradation mechanism which affects analog and mixed signal circuits (AMS) as transistor operates continuously in saturation condition. New model is proposed to account for e-e scattering in advanced technology nodes due to high gate electric field. The model is validated with 28nm and 65nm thick oxide data for different stress voltages. It demonstrates shift in worst case CHC condition to Vgs=Vds from Vgs=0.5Vds. A novel iteration based aging simulation framework for AMS designs is proposed which eliminates limitation for conventional reliability tools. This approach helps us identify a unique positive feedback mechanism termed as Bias Runaway. Bias runaway, is rapid increase of the bias voltage in AMS circuits which occurs when the feedback between the bias current and the effect of channel hot carrier turns into positive. The degradation of CHC is a gradual process but under specific circumstances, the degradation rate can be dramatically accelerated. Such a catastrophic phenomenon is highly sensitive to the initial operation condition, as well as transistor gate length. Based on 65nm silicon data, our work investigates the critical condition that triggers bias runaway, and the impact of gate length tuning. We develop new compact models as well as the simulation methodology for circuit diagnosis, and propose design solutions and the trade-offs to avoid bias runaway, which is vitally important to reliable AMS designs.
Channel hot carrier (CHC) is another dominant degradation mechanism which affects analog and mixed signal circuits (AMS) as transistor operates continuously in saturation condition. New model is proposed to account for e-e scattering in advanced technology nodes due to high gate electric field. The model is validated with 28nm and 65nm thick oxide data for different stress voltages. It demonstrates shift in worst case CHC condition to Vgs=Vds from Vgs=0.5Vds. A novel iteration based aging simulation framework for AMS designs is proposed which eliminates limitation for conventional reliability tools. This approach helps us identify a unique positive feedback mechanism termed as Bias Runaway. Bias runaway, is rapid increase of the bias voltage in AMS circuits which occurs when the feedback between the bias current and the effect of channel hot carrier turns into positive. The degradation of CHC is a gradual process but under specific circumstances, the degradation rate can be dramatically accelerated. Such a catastrophic phenomenon is highly sensitive to the initial operation condition, as well as transistor gate length. Based on 65nm silicon data, our work investigates the critical condition that triggers bias runaway, and the impact of gate length tuning. We develop new compact models as well as the simulation methodology for circuit diagnosis, and propose design solutions and the trade-offs to avoid bias runaway, which is vitally important to reliable AMS designs.
ContributorsSutaria, Ketul (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Chakrabarti, Chaitali (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Created2014
Description
Several state of the art, monitoring and control systems, such as DC motor
controllers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.
controllers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.
ContributorsThirunakkarasu, Shankar (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Kozicki, Michael (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014