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- Genre: Academic theses
- Creators: Bakkaloglu, Bertan
- Creators: Vittal, Vijay
- Status: Published
Description
Insulation aging monitoring is widely used to evaluate the operating condition of power equipment. One important monitoring method is detecting partial discharges (PD). PD is a localized breakdown of dielectric and its characteristics can give information about the insulation aging. Most existing test methods cannot identify different kinds of defects. Also, the practical application of PD detection in most existing test methods is restricted by weak PD signals and strong electric field disturbance from surroundings. In order to monitor aging situation in detail, types of PDs are important features to take into account. To classify different types of PDs, pulse sequence analysis (PSA) method is advocated to analyze PDs in the rod-plane model. This method can reflect cumulative effects of PDs, which are always ignored when only measuring PD value. It also shows uniform characteristics when different kinds of detecting system are utilized. Moreover, it does not need calibration. Analysis results from PSA show highly consistent distribution patterns for the same type of PDs and significant differences in the distribution patterns among types of PDs. Furthermore, a new method to detect PD signals using fiber bragg grating (FBG) based PD sensor is studied in this research. By using a piezoelectric ceramic transducer (PZT), small PD signals can be converted to pressure signal and then converted to an optical wavelength signal with FBG. The optical signal is isolated from the electric field; therefore its attenuation and anti-jamming performance will be better than traditional methods. Two sensors, one with resonant frequency of 42.7 kHz and the other 300 kHz, were used to explore the performance of this testing system. However, there were issues with the sensitivity of the sensors of these devices and the results have been communicated with the company. These devices could not give the results at the same level of accuracy as the conventional methods.
ContributorsCui, Longfei (Author) / Gorur, Ravi (Thesis advisor) / Vittal, Vijay (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2013
Description
The applications which use MEMS accelerometer have been on rise and many new fields which are using the MEMS devices have been on rise. The industry is trying to reduce the cost of production of these MEMS devices. These devices are manufactured using micromachining and the interface circuitry is manufactured using CMOS and the final product is integrated on to a single chip. Amount spent on testing of the MEMS devices make up a considerable share of the total final cost of the device. In order to save the cost and time spent on testing, researchers have been trying to develop different methodologies. At present, MEMS devices are tested using mechanical stimuli to measure the device parameters and for calibration the device. This testing is necessary since the MEMS process is not a very well controlled process unlike CMOS. This is done using an ATE and the cost of using ATE (automatic testing equipment) contribute to 30-40% of the devices final cost. This thesis proposes an architecture which can use an Electrical Signal to stimulate the MEMS device and use the data from the MEMS response in approximating the calibration coefficients efficiently. As a proof of concept, we have designed a BIST (Built-in self-test) circuit for MEMS accelerometer. The BIST has an electrical stimulus generator, Capacitance-to-voltage converter, ∑ ∆ ADC. This thesis explains in detail the design of the Electrical stimulus generator. We have also designed a technique to correlate the parameters obtained from electrical stimuli to those obtained by mechanical stimuli. This method is cost effective since the additional circuitry needed to implement BIST is less since the technique utilizes most of the existing standard readout circuitry already present.
ContributorsJangala Naga, Naveen Sai (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2014
Description
Switch mode DC/DC converters are suited for battery powered applications, due to their high efficiency, which help in conserving the battery lifetime. Fixed Frequency PWM based converters, which are generally used for these applications offer good voltage regulation, low ripple and excellent efficiency at high load currents. However at light load currents, fixed frequency PWM converters suffer from poor efficiencies The PFM control offers higher efficiency at light loads at the cost of a higher ripple. The PWM has a poor efficiency at light loads but good voltage ripple characteristics, due to a high switching frequency. To get the best of both control modes, both loops are used together with the control switched from one loop to another based on the load current. Such architectures are referred to as hybrid converters. While transition from PFM to PWM loop can be made by estimating the average load current, transition from PFM to PWM requires voltage or peak current sensing. This theses implements a hysteretic PFM solution for a synchronous buck converter with external MOSFET's, to achieve efficiencies of about 80% at light loads. As the PFM loop operates independently of the PWM loop, a transition circuit for automatically transitioning from PFM to PWM is implemented. The transition circuit is implemented digitally without needing any external voltage or current sensing circuit.
ContributorsVivek, Parasuram (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ogras, Umit Y. (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2014
Description
This dissertation considers an integrated approach to system design and controller design based on analyzing limits of system performance. Historically, plant design methodologies have not incorporated control relevant considerations. Such an approach could result in a system that might not meet its specifications (or one that requires a complex control architecture to do so). System and controller designers often go through several iterations in order to converge to an acceptable plant and controller design. The focus of this dissertation is on the design and control an air-breathing hypersonic vehicle using such an integrated system-control design framework. The goal is to reduce the number of system-control design iterations (by explicitly incorporate control considerations in the system design process), as well as to influence the guidance/trajectory specifications for the system. Due to the high computational costs associated with obtaining a dynamic model for each plant configuration considered, approximations to the system dynamics are used in the control design process. By formulating the control design problem using bilinear and polynomial matrix inequalities, several common control and system design constraints can be simultaneously incorporated into a vehicle design optimization. Several design problems are examined to illustrate the effectiveness of this approach (and to compare the computational burden of this methodology against more traditional approaches).
ContributorsSridharan, Srikanth (Author) / Rodriguez, Armando A (Thesis advisor) / Mittelmann, Hans D (Committee member) / Si, Jennie (Committee member) / Tsakalis, Konstantinos S (Committee member) / Arizona State University (Publisher)
Created2014
Description
ABSTRACT The D flip flop acts as a sequencing element while designing any pipelined system. Radiation Hardening by Design (RHBD) allows hardened circuits to be fabricated on commercially available CMOS manufacturing process. Recently, single event transients (SET's) have become as important as single event upset (SEU) in radiation hardened high speed digital designs. A novel temporal pulse based RHBD flip-flop design is presented. Temporally delayed pulses produced by a radiation hardened pulse generator design samples the data in three redundant pulse latches. The proposed RHBD flip-flop has been statistically designed and fabricated on 90 nm TSMC LP process. Detailed simulations of the flip-flop operation in both normal and radiation environments are presented. Spatial separation of critical nodes for the physical design of the flip-flop is carried out for mitigating multi-node charge collection upsets. The proposed flip-flop is also used in commercial CAD flows for high performance chip designs. The proposed flip-flop is used in the design and auto-place-route (APR) of an advanced encryption system and the metrics analyzed.
ContributorsKumar, Sushil (Author) / Clark, Lawrence (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2014
Description
In modern electric power systems, energy management systems (EMSs) are responsi-ble for monitoring and controlling the generation system and transmission networks. State estimation (SE) is a critical `must run successful' component within the EMS software. This is dictated by the high reliability requirements and need to represent the closest real time model for market operations and other critical analysis functions in the EMS. Tradi-tionally, SE is run with data obtained only from supervisory control and data acquisition (SCADA) devices and systems. However, more emphasis on improving the performance of SE drives the inclusion of phasor measurement units (PMUs) into SE input data. PMU measurements are claimed to be more accurate than conventional measurements and PMUs `time stamp' measurements accurately. These widely distributed devices meas-ure the voltage phasors directly. That is, phase information for measured voltages and currents are available. PMUs provide data time stamps to synchronize measurements. Con-sidering the relatively small number of PMUs installed in contemporary power systems in North America, performing SE with only phasor measurements is not feasible. Thus a hy-brid SE, including both SCADA and PMU measurements, is the reality for contemporary power system SE. The hybrid approach is the focus of a number of research papers. There are many practical challenges in incorporating PMUs into SE input data. The higher reporting rates of PMUs as compared with SCADA measurements is one of the salient problems. The disparity of reporting rates raises a question whether buffering the phasor measurements helps to give better estimates of the states. The research presented in this thesis addresses the design of data buffers for PMU data as used in SE applications in electric power systems. The system theoretic analysis is illustrated using an operating electric power system in the southwest part of the USA. Var-ious instances of state estimation data have been used for analysis purposes. The details of the research, results obtained and conclusions drawn are presented in this document.
ContributorsMurugesan, Veerakumar (Author) / Vittal, Vijay (Committee member) / Heydt, Gerald (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2013
Description
The basal ganglia are four sub-cortical nuclei associated with motor control and reward learning. They are part of numerous larger mostly segregated loops where the basal ganglia receive inputs from specific regions of cortex. Converging on these inputs are dopaminergic neurons that alter their firing based on received and/or predicted rewarding outcomes of a behavior. The basal ganglia's output feeds through the thalamus back to the areas of the cortex where the loop originated. Understanding the dynamic interactions between the various parts of these loops is critical to understanding the basal ganglia's role in motor control and reward based learning. This work developed several experimental techniques that can be applied to further study basal ganglia function. The first technique used micro-volume injections of low concentration muscimol to decrease the firing rates of recorded neurons in a limited area of cortex in rats. Afterwards, an artificial cerebrospinal fluid flush was injected to rapidly eliminate the muscimol's effects. This technique was able to contain the effects of muscimol to approximately a 1 mm radius volume and limited the duration of the drug effect to less than one hour. This technique could be used to temporarily perturb a small portion of the loops involving the basal ganglia and then observe how these effects propagate in other connected regions. The second part applied self-organizing maps (SOM) to find temporal patterns in neural firing rate that are independent of behavior. The distribution of detected patterns frequency on these maps can then be used to determine if changes in neural activity are occurring over time. The final technique focused on the role of the basal ganglia in reward learning. A new conditioning technique was created to increase the occurrence of selected patterns of neural activity without utilizing any external reward or behavior. A pattern of neural activity in the cortex of rats was selected using an SOM. The pattern was then reinforced by being paired with electrical stimulation of the medial forebrain bundle triggering dopamine release in the basal ganglia. Ultimately, this technique proved unsuccessful possibly due to poor selection of the patterns being reinforced.
ContributorsBaldwin, Nathan Aaron (Author) / Helms Tillery, Stephen I (Thesis advisor) / Castaneda, Edward (Committee member) / Buneo, Christopher A (Committee member) / Muthuswamy, Jitendran (Committee member) / Si, Jennie (Committee member) / Arizona State University (Publisher)
Created2014
Description
Sliding-Mode Control (SMC) has several benefits over traditional Proportional-Integral-Differential (PID) control in terms of fast transient response, robustness to parameter and component variations, and low sensitivity to loop disturbances. An All-Digital Sliding-Mode (ADSM) controlled DC-DC converter, utilizing single-bit oversampled frequency domain digitizers is proposed. In the proposed approach, feedback and reference digitizing Analog-to-Digital Converters (ADC) are based on a single-bit, first order Sigma-Delta frequency to digital converter, running at 32MHz over-sampling rate. The ADSM regulator achieves 1% settling time in less than 5uSec for a load variation of 600mA. The sliding-mode controller utilizes a high-bandwidth hysteretic differentiator and an integrator to perform the sliding control law in digital domain. The proposed approach overcomes the steady state error (or DC offset), and limits the switching frequency range, which are the two common problems associated with sliding-mode controllers. The IC is designed and fabricated on a 0.35um CMOS process occupying an active area of 2.72mm-squared. Measured peak efficiency is 83%.
ContributorsDashtestani, Ahmad (Author) / Bakkaloglu, Bertan (Thesis advisor) / Thornton, Trevor (Committee member) / Song, Hongjiang (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
Description
Non-volatile memories (NVM) are widely used in modern electronic devices due to their non-volatility, low static power consumption and high storage density. While Flash memories are the dominant NVM technology, resistive memories such as phase change access memory (PRAM) and spin torque transfer random access memory (STT-MRAM) are gaining ground. All these technologies suffer from reliability degradation due to process variations, structural limits and material property shift. To address the reliability concerns of these NVM technologies, multi-level low cost solutions are proposed for each of them. My approach consists of first building a comprehensive error model. Next the error characteristics are exploited to develop low cost multi-level strategies to compensate for the errors. For instance, for NAND Flash memory, I first characterize errors due to threshold voltage variations as a function of the number of program/erase cycles. Next a flexible product code is designed to migrate to a stronger ECC scheme as program/erase cycles increases. An adaptive data refresh scheme is also proposed to improve memory reliability with low energy cost for applications with different data update frequencies. For PRAM, soft errors and hard errors models are built based on shifts in the resistance distributions. Next I developed a multi-level error control approach involving bit interleaving and subblock flipping at the architecture level, threshold resistance tuning at the circuit level and programming current profile tuning at the device level. This approach helped reduce the error rate significantly so that it was now sufficient to use a low cost ECC scheme to satisfy the memory reliability constraint. I also studied the reliability of a PRAM+DRAM hybrid memory system and analyzed the tradeoffs between memory performance, programming energy and lifetime. For STT-MRAM, I first developed an error model based on process variations. I developed a multi-level approach to reduce the error rates that consisted of increasing the W/L ratio of the access transistor, increasing the voltage difference across the memory cell and adjusting the current profile during write operation. This approach enabled use of a low cost BCH based ECC scheme to achieve very low block failure rates.
ContributorsYang, Chengen (Author) / Chakrabarti, Chaitali (Thesis advisor) / Cao, Yu (Committee member) / Ogras, Umit Y. (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2014
Description
This study focuses on state estimation of nonlinear discrete time systems with constraints. Physical processes have inherent in them, constraints on inputs, outputs, states and disturbances. These constraints can provide additional information to the estimator in estimating states from the measured output. Recursive filters such as Kalman Filters or Extended Kalman Filters are commonly used in state estimation; however, they do not allow inclusion of constraints in their formulation. On the other hand, computational complexity of full information estimation (using all measurements) grows with iteration and becomes intractable. One way of formulating the recursive state estimation problem with constraints is the Moving Horizon Estimation (MHE) approximation. Estimates of states are calculated from the solution of a constrained optimization problem of fixed size. Detailed formulation of this strategy is studied and properties of this estimation algorithm are discussed in this work. The problem with the MHE formulation is solving an optimization problem in each iteration which is computationally intensive. State estimation with constraints can be formulated as Extended Kalman Filter (EKF) with a projection applied to estimates. The states are estimated from the measurements using standard Extended Kalman Filter (EKF) algorithm and the estimated states are projected on to a constrained set. Detailed formulation of this estimation strategy is studied and the properties associated with this algorithm are discussed. Both these state estimation strategies (MHE and EKF with projection) are tested with examples from the literature. The average estimation time and the sum of square estimation error are used to compare performance of these estimators. Results of the case studies are analyzed and trade-offs are discussed.
ContributorsJoshi, Rakesh (Author) / Tsakalis, Konstantinos (Thesis advisor) / Rodriguez, Armando (Committee member) / Si, Jennie (Committee member) / Arizona State University (Publisher)
Created2013