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- Genre: Academic theses
- Genre: Masters Thesis
- Creators: Bakkaloglu, Bertan
- Creators: Yu, Hongbin
Description
Photovoltaic (PV) systems are affected by converter losses, partial shading and other mismatches in the panels. This dissertation introduces a sub-panel maximum power point tracking (MPPT) architecture together with an integrated CMOS current sensor circuit on a chip to reduce the mismatch effects, losses and increase the efficiency of the PV system. The sub-panel MPPT increases the efficiency of the PV during the shading and replaces the bypass diodes in the panels with an integrated MPPT and DC-DC regulator. For the integrated MPPT and regulator, the research developed an integrated standard CMOS low power and high common mode range Current-to-Digital Converter (IDC) circuit and its application for DC-DC regulator and MPPT. The proposed charge based CMOS switched-capacitor circuit directly digitizes the output current of the DC-DC regulator without an analog-to-digital converter (ADC) and the need for high-voltage process technology. Compared to the resistor based current-sensing methods that requires current-to-voltage circuit, gain block and ADC, the proposed CMOS IDC is a low-power efficient integrated circuit that achieves high resolution, lower complexity, and lower power consumption. The IDC circuit is fabricated on a 0.7 um CMOS process, occupies 2mm x 2mm and consumes less than 27mW. The IDC circuit has been tested and used for boost DC-DC regulator and MPPT for photo-voltaic system. The DC-DC converter has an efficiency of 95%. The sub-module level power optimization improves the output power of a shaded panel by up to 20%, compared to panel MPPT with bypass diodes.
ContributorsMarti-Arbona, Edgar (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2014
Description
Modern day deep sub-micron SOC architectures often demand very low supply noise levels. As supply voltage decreases with decreasing deep sub-micron gate length, noise on the power supply starts playing a dominant role in noise-sensitive analog blocks, especially high precision ADC, PLL, and RF SOC's. Most handheld and portable applications and highly sensitive medical instrumentation circuits tend to use low noise regulators as on-chip or on board power supply. Nonlinearities associated with LNA's, mixers and oscillators up-convert low frequency noise with the signal band. Specifically, synthesizer and TCXO phase noise, LNA and mixer noise figure, and adjacent channel power ratios of the PA are heavily influenced by the supply noise and ripple. This poses a stringent requirement on a very low noise power supply with high accuracy and fast transient response. Low Dropout (LDO) regulators are preferred over switching regulators for these applications due to their attractive low noise and low ripple features. LDO's shield sensitive blocks from high frequency fluctuations on the power supply while providing high accuracy, fast response supply regulation.
This research focuses on developing innovative techniques to reduce the noise of any generic wideband LDO, stable with or without load capacitor. The proposed techniques include Switched RC Filtering to reduce the Bandgap Reference noise, Current Mode Chopping to reduce the Error Amplifier noise & MOS-R based RC filter to reduce the noise due to bias current. The residual chopping ripple was reduced using a Switched Capacitor notch filter. Using these techniques, the integrated noise of a wideband LDO was brought down to 15µV in the integration band of 10Hz to 100kHz. These techniques can be integrated into any generic LDO without any significant area overhead.
This research focuses on developing innovative techniques to reduce the noise of any generic wideband LDO, stable with or without load capacitor. The proposed techniques include Switched RC Filtering to reduce the Bandgap Reference noise, Current Mode Chopping to reduce the Error Amplifier noise & MOS-R based RC filter to reduce the noise due to bias current. The residual chopping ripple was reduced using a Switched Capacitor notch filter. Using these techniques, the integrated noise of a wideband LDO was brought down to 15µV in the integration band of 10Hz to 100kHz. These techniques can be integrated into any generic LDO without any significant area overhead.
ContributorsMagod Ramakrishna, Raveesh (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
Inductors are fundamental components that do not scale well. Their physical limitations to scalability along with their inherent losses make them the main obstacle in achieving monolithic system-on-chip platform (SoCP). For past decades researchers focused on integrating magnetic materials into on-chip inductors in the quest of achieving high inductance density and quality factor (QF). The state of the art on-chip inductor is made of an enclosed magnetic thin-film around the current carrying wire for maximum flux amplification. Though the integration of magnetic materials results in enhanced inductor characteristics, this approach has its own challenges and limitations especially in power applications. The current-induced magnetic field (HDC) drives the magnetic film into its saturation state. At saturation, inductance and QF drop to that of air-core inductors, eliminating the benefits of integrating magnetic materials. Increasing the current carrying capability without substantially sacrificing benefits brought on by the magnetic material is an open challenge in power applications. Researchers continue to address this challenge along with the continuous improvement in inductance and QF for RF and power applications.
In this work on-chip inductors incorporating magnetic Co-4%Zr-4%Ta -8%B thin films were fabricated and their characteristics were examined under the influence of an externally applied DC magnetic field. It is well established that spins in magnetic materials tend to align themselves in the same direction as the applied field. The resistance of the inductor resulting from the ferromagnetic film can be changed by manipulating the orientation of magnetization. A reduction in resistance should lead to decreases in losses and an enhancement in the QF. The effect of externally applied DC magnetic field along the easy and hard axes was thoroughly investigated. Depending on the strength and orientation of the externally applied field significant improvements in QF response were gained at the expense of a relative reduction in inductance. Characteristics of magnetic-based inductors degrade with current-induced stress. It was found that applying an externally low DC magnetic field across the on-chip inductor prevents the degradation in inductance and QF responses. Examining the effect of DC magnetic field on current carrying capability under low temperature is suggested.
In this work on-chip inductors incorporating magnetic Co-4%Zr-4%Ta -8%B thin films were fabricated and their characteristics were examined under the influence of an externally applied DC magnetic field. It is well established that spins in magnetic materials tend to align themselves in the same direction as the applied field. The resistance of the inductor resulting from the ferromagnetic film can be changed by manipulating the orientation of magnetization. A reduction in resistance should lead to decreases in losses and an enhancement in the QF. The effect of externally applied DC magnetic field along the easy and hard axes was thoroughly investigated. Depending on the strength and orientation of the externally applied field significant improvements in QF response were gained at the expense of a relative reduction in inductance. Characteristics of magnetic-based inductors degrade with current-induced stress. It was found that applying an externally low DC magnetic field across the on-chip inductor prevents the degradation in inductance and QF responses. Examining the effect of DC magnetic field on current carrying capability under low temperature is suggested.
ContributorsKhdour, Mahmoud (Author) / Yu, Hongbin (Thesis advisor) / Pan, George (Committee member) / Goryll, Michael (Committee member) / Bearat, Hamdallah (Committee member) / Arizona State University (Publisher)
Created2014
Description
The aging process due to Bias Temperature Instability (both NBTI and PBTI) and Channel Hot Carrier (CHC) is a key limiting factor of circuit lifetime in CMOS design. Threshold voltage shift due to BTI is a strong function of stress voltage and temperature complicating stress and recovery prediction. This poses a unique challenge for long-term aging prediction for wide range of stress patterns. Traditional approaches usually resort to an average stress waveform to simplify the lifetime prediction. They are efficient, but fail to capture circuit operation, especially under dynamic voltage scaling (DVS) or in analog/mixed signal designs where the stress waveform is much more random. This work presents a suite of modelling solutions for BTI that enable aging simulation under all possible stress conditions. Key features of this work are compact models to predict BTI aging based on Reaction-Diffusion theory when the stress voltage is varying. The results to both reaction-diffusion (RD) and trapping-detrapping (TD) mechanisms are presented to cover underlying physics. Silicon validation of these models is performed at 28nm, 45nm and 65nm technology nodes, at both device and circuit levels. Efficient simulation leveraging the BTI models under DVS and random input waveform is applied to both digital and analog representative circuits such as ring oscillators and LNA. Both physical mechanisms are combined into a unified model which improves prediction accuracy at 45nm and 65nm nodes. Critical failure condition is also illustrated based on NBTI and PBTI at 28nm. A comprehensive picture for duty cycle shift is shown. DC stress under clock gating schemes results in monotonic shift in duty cycle which an AC stress causes duty cycle to converge close to 50% value. Proposed work provides a general and comprehensive solution to aging analysis under random stress patterns under BTI.
Channel hot carrier (CHC) is another dominant degradation mechanism which affects analog and mixed signal circuits (AMS) as transistor operates continuously in saturation condition. New model is proposed to account for e-e scattering in advanced technology nodes due to high gate electric field. The model is validated with 28nm and 65nm thick oxide data for different stress voltages. It demonstrates shift in worst case CHC condition to Vgs=Vds from Vgs=0.5Vds. A novel iteration based aging simulation framework for AMS designs is proposed which eliminates limitation for conventional reliability tools. This approach helps us identify a unique positive feedback mechanism termed as Bias Runaway. Bias runaway, is rapid increase of the bias voltage in AMS circuits which occurs when the feedback between the bias current and the effect of channel hot carrier turns into positive. The degradation of CHC is a gradual process but under specific circumstances, the degradation rate can be dramatically accelerated. Such a catastrophic phenomenon is highly sensitive to the initial operation condition, as well as transistor gate length. Based on 65nm silicon data, our work investigates the critical condition that triggers bias runaway, and the impact of gate length tuning. We develop new compact models as well as the simulation methodology for circuit diagnosis, and propose design solutions and the trade-offs to avoid bias runaway, which is vitally important to reliable AMS designs.
Channel hot carrier (CHC) is another dominant degradation mechanism which affects analog and mixed signal circuits (AMS) as transistor operates continuously in saturation condition. New model is proposed to account for e-e scattering in advanced technology nodes due to high gate electric field. The model is validated with 28nm and 65nm thick oxide data for different stress voltages. It demonstrates shift in worst case CHC condition to Vgs=Vds from Vgs=0.5Vds. A novel iteration based aging simulation framework for AMS designs is proposed which eliminates limitation for conventional reliability tools. This approach helps us identify a unique positive feedback mechanism termed as Bias Runaway. Bias runaway, is rapid increase of the bias voltage in AMS circuits which occurs when the feedback between the bias current and the effect of channel hot carrier turns into positive. The degradation of CHC is a gradual process but under specific circumstances, the degradation rate can be dramatically accelerated. Such a catastrophic phenomenon is highly sensitive to the initial operation condition, as well as transistor gate length. Based on 65nm silicon data, our work investigates the critical condition that triggers bias runaway, and the impact of gate length tuning. We develop new compact models as well as the simulation methodology for circuit diagnosis, and propose design solutions and the trade-offs to avoid bias runaway, which is vitally important to reliable AMS designs.
ContributorsSutaria, Ketul (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Chakrabarti, Chaitali (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Created2014
Description
Several state of the art, monitoring and control systems, such as DC motor
controllers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.
controllers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.
ContributorsThirunakkarasu, Shankar (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Kozicki, Michael (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
Group III-nitride semiconductors have been commercially used in the fabrication of light-emitting diodes and laser diodes, covering the ultraviolet-visible-infrared spectral range and exhibit unique properties suitable for modern optoelectronic applications. InGaN ternary alloys have energy band gaps ranging from 0.7 to 3.4 eV. It has a great potential in the application for high efficient solar cells. AlGaN ternary alloys have energy band gaps ranging from 3.4 to 6.2 eV. These alloys have a great potential in the application of deep ultra violet laser diodes. However, there are still many issues with these materials that remain to be solved. In this dissertation, several issues concerning structural, electronic, and optical properties of III-nitrides have been investigated using transmission electron microscopy. First, the microstructure of InxGa1-xN (x = 0.22, 0.46, 0.60, and 0.67) films grown by metal-modulated epitaxy on GaN buffer /sapphire substrates is studied. The effect of indium composition on the structure of InGaN films and strain relaxation is carefully analyzed. High luminescence intensity, low defect density, and uniform full misfit strain relaxation are observed for x = 0.67. Second, the properties of high-indium-content InGaN thin films using a new molecular beam epitaxy method have been studied for applications in solar cell technologies. This method uses a high quality AlN buffer with large lattice mismatch that results in a critical thickness below one lattice parameter. Finally, the effect of different substrates and number of gallium sources on the microstructure of AlGaN-based deep ultraviolet laser has been studied. It is found that defects in epitaxial layer are greatly reduced when the structure is deposited on a single crystal AlN substrate. Two gallium sources in the growth of multiple quantum wells active region are found to cause a significant improvement in the quality of quantum well structures.
ContributorsWei, Yong (Author) / Ponce, Fernando (Thesis advisor) / Chizmeshya, Andrew (Committee member) / McCartney, Martha (Committee member) / Menéndez, Jose (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2014
Description
High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
ContributorsJankunas, Benjamin (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2014
Description
Switching Converters (SC) are an excellent choice for hand held devices due to their high power conversion efficiency. However, they suffer from two major drawbacks. The first drawback is that their dynamic response is sensitive to variations in inductor (L) and capacitor (C) values. A cost effective solution is implemented by designing a programmable digital controller. Despite variations in L and C values, the target dynamic response can be achieved by computing and programming the filter coefficients for a particular L and C. Besides, digital controllers have higher immunity to environmental changes such as temperature and aging of components. The second drawback of SCs is their poor efficiency during low load conditions if operated in Pulse Width Modulation (PWM) mode. However, if operated in Pulse Frequency Modulation (PFM) mode, better efficiency numbers can be achieved. A mostly-digital way of detecting PFM mode is implemented. Besides, a slow serial interface to program the chip, and a high speed serial interface to characterize mixed signal blocks as well as to ship data in or out for debug purposes are designed. The chip is taped out in 0.18µm IBM's radiation hardened CMOS process technology. A test board is built with the chip, external power FETs and driver IC. At the time of this writing, PWM operation, PFM detection, transitions between PWM and PFM, and both serial interfaces are validated on the test board.
ContributorsMumma Reddy, Abhiram (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ogras, Umit Y. (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2014
Description
This dissertation aims to demonstrate a new approach to fabricating solar cells for spectrum-splitting photovoltaic systems with the potential to reduce their cost and complexity of manufacturing, called Monolithically Integrated Laterally Arrayed Multiple Band gap (MILAMB) solar cells. Single crystal semiconductor alloy nanowire (NW) ensembles are grown with the alloy composition and band gap changing continuously across a broad range over the surface of a single substrate in a single, inexpensive growth step by the Dual-Gradient Method. The nanowire ensembles then serve as the absorbing materials in a set of solar cells for spectrum-splitting photovoltaic systems.
Preliminary design and simulation studies based on Anderson's model band line-ups were undertaken for CdPbS and InGaN alloys. Systems of six subcells obtained efficiencies in the 32-38% range for CdPbS and 34-40% for InGaN at 1-240 suns, though both materials systems require significant development before these results could be achieved experimentally. For an experimental demonstration, CdSSe was selected due to its availability. Proof-of-concept CdSSe nanowire ensemble solar cells with two subcells were fabricated simultaneously on one substrate. I-V characterization under 1 sun AM1.5G conditions yielded open-circuit voltages (Voc) up to 307 and 173 mV and short-circuit current densities (Jsc) up to 0.091 and 0.974 mA/cm2 for the CdS- and CdSe-rich cells, respectively. Similar thin film cells were also fabricated for comparison. The nanowire cells showed substantially higher Voc than the film cells, which was attributed to higher material quality in the CdSSe absorber. I-V measurements were also conducted with optical filters to simulate a simple form of spectrum-splitting. The CdS-rich cells showed uniformly higher Voc and fill factor (FF) than the CdSe-rich cells, as expected due to their larger band gaps. This suggested higher power density was produced by the CdS-rich cells on the single-nanowire level, which is the principal benefit of spectrum-splitting. These results constitute a proof-of-concept experimental demonstration of the MILAMB approach to fabricating multiple cells for spectrum-splitting photovoltaics. Future systems based on this approach could help to reduce the cost and complexity of manufacturing spectrum-splitting photovoltaic systems and offer a low cost alternative to multi-junction tandems for achieving high efficiencies.
Preliminary design and simulation studies based on Anderson's model band line-ups were undertaken for CdPbS and InGaN alloys. Systems of six subcells obtained efficiencies in the 32-38% range for CdPbS and 34-40% for InGaN at 1-240 suns, though both materials systems require significant development before these results could be achieved experimentally. For an experimental demonstration, CdSSe was selected due to its availability. Proof-of-concept CdSSe nanowire ensemble solar cells with two subcells were fabricated simultaneously on one substrate. I-V characterization under 1 sun AM1.5G conditions yielded open-circuit voltages (Voc) up to 307 and 173 mV and short-circuit current densities (Jsc) up to 0.091 and 0.974 mA/cm2 for the CdS- and CdSe-rich cells, respectively. Similar thin film cells were also fabricated for comparison. The nanowire cells showed substantially higher Voc than the film cells, which was attributed to higher material quality in the CdSSe absorber. I-V measurements were also conducted with optical filters to simulate a simple form of spectrum-splitting. The CdS-rich cells showed uniformly higher Voc and fill factor (FF) than the CdSe-rich cells, as expected due to their larger band gaps. This suggested higher power density was produced by the CdS-rich cells on the single-nanowire level, which is the principal benefit of spectrum-splitting. These results constitute a proof-of-concept experimental demonstration of the MILAMB approach to fabricating multiple cells for spectrum-splitting photovoltaics. Future systems based on this approach could help to reduce the cost and complexity of manufacturing spectrum-splitting photovoltaic systems and offer a low cost alternative to multi-junction tandems for achieving high efficiencies.
ContributorsCaselli, Derek (Author) / Ning, Cun-Zheng (Thesis advisor) / Tao, Meng (Committee member) / Yu, Hongbin (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2014
Description
As residential photovoltaic (PV) systems become more and more common and widespread, their system architectures are being developed to maximize power extraction while keeping the cost of associated electronics to a minimum. An architecture that has become popular in recent years is the "DC optimizer" architecture, wherein one DC-DC converter is connected to the output of each PV module. The DC optimizer architecture has the advantage of performing maximum power-point tracking (MPPT) at the module level, without the high cost of using an inverter on each module (the "microinverter" architecture). This work details the design of a proposed DC optimizer. The design incorporates a series-input parallel-output topology to implement MPPT at the sub-module level. This topology has some advantages over the more common series-output DC optimizer, including relaxed requirements for the system's inverter. An autonomous control scheme is proposed for the series-connected converters, so that no external control signals are needed for the system to operate, other than sunlight. The DC optimizer in this work is designed with an emphasis on efficiency, and to that end it uses GaN FETs and an active clamp technique to reduce switching and conduction losses. As with any parallel-output converter, phase interleaving is essential to minimize output RMS current losses. This work proposes a novel phase-locked loop (PLL) technique to achieve interleaving among the series-input converters.
ContributorsLuster, Daniel (Author) / Ayyanar, Raja (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2014