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- All Subjects: Electromagnetic waves--Scattering.
- Creators: Aberle, James T.
Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
Electromagnetic band-gap (EBG) structures have noteworthy electromagnetic characteristics that include their phase variations with frequency. When combining perfect electric conductor (PEC) and EBG structures on the same ground plane, the scattering fields of the ground plane are altered because of the scattering properties of EBG structures. The scattering fields are cancelled along the principal planes because PEC and EBG structures are anti-phase at the resonant frequency. To make the scattered fields symmetrical under plane wave incidence, a square checkerboard surface is designed to form constructive and destructive interference scattering patterns to reduce the intensity of the scattered fields toward the observer; thus reducing the radar cross section (RCS). To increase the 10-dB RCS reduction (compared to a PEC surface) bandwidth, checkerboard surfaces of two different EBG structures on the same ground plane are designed. Thus, significant RCS reduction over a wider frequency bandwidth of about 63% is achieved.
Another design is a hexagonal checkerboard surface that achieves the same RCS reduction bandwidth because it combines the same EBG designs. The hexagonal checkerboard design further reduce the RCS than square checkerboard designs because the reflected energy is re-directed toward six directions and a null remains in the normal direction.
A dual frequency band checkerboard surface with 10-dB RCS reduction bandwidths of 61% and 24% is realized by utilizing two dual-band EBG structures, while the surfaces maintain scattering in four quadrants. The first RCS reduction bandwidth of the dual band is basically the same as in the square checkerboard design; however, the present surface exhibits a second frequency band of 10-dB RCS reduction.
Finally, cylindrically curved checkerboard surfaces are designed and examined for three different radii of curvature. Both narrow and wide band curved checkerboard surfaces are evaluated under normal incidence for both horizontal and vertical polarizations. Simulated bistatic RCS patterns of the cylindrical checkerboard surfaces are presented.
For all designs, bistatic and monostatic RCS of each checkerboard surface design are compared to that of the corresponding PEC surface. The monostatic simulations are also compared with measurements as a function of frequency and polarization. A very good agreement has been attained throughout.
Another design is a hexagonal checkerboard surface that achieves the same RCS reduction bandwidth because it combines the same EBG designs. The hexagonal checkerboard design further reduce the RCS than square checkerboard designs because the reflected energy is re-directed toward six directions and a null remains in the normal direction.
A dual frequency band checkerboard surface with 10-dB RCS reduction bandwidths of 61% and 24% is realized by utilizing two dual-band EBG structures, while the surfaces maintain scattering in four quadrants. The first RCS reduction bandwidth of the dual band is basically the same as in the square checkerboard design; however, the present surface exhibits a second frequency band of 10-dB RCS reduction.
Finally, cylindrically curved checkerboard surfaces are designed and examined for three different radii of curvature. Both narrow and wide band curved checkerboard surfaces are evaluated under normal incidence for both horizontal and vertical polarizations. Simulated bistatic RCS patterns of the cylindrical checkerboard surfaces are presented.
For all designs, bistatic and monostatic RCS of each checkerboard surface design are compared to that of the corresponding PEC surface. The monostatic simulations are also compared with measurements as a function of frequency and polarization. A very good agreement has been attained throughout.
ContributorsChen, Wengang (Author) / Balanis, Constantine A. (Thesis advisor) / Aberle, James T. (Committee member) / Yu, Hongbin (Committee member) / Palais, Joseph C. (Committee member) / Arizona State University (Publisher)
Created2016