Matching Items (2)
Filtering by

Clear all filters

151945-Thumbnail Image.png
Description
In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a

In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.
ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Created2013
153212-Thumbnail Image.png
Description
This dissertation explores the megamachine, a prominent metaphor in American humanist and philosopher of technology, Lewis Mumford's Myth of the Machine series. The term refers critically to dynamic, regimented human capacities that drive scientific and technical innovation in society. Mumford's view of the nature of collectives focuses on qualities and

This dissertation explores the megamachine, a prominent metaphor in American humanist and philosopher of technology, Lewis Mumford's Myth of the Machine series. The term refers critically to dynamic, regimented human capacities that drive scientific and technical innovation in society. Mumford's view of the nature of collectives focuses on qualities and patterns that emerge from the behavior of groups, societies, systems, and ecologies. It is my aim to reenergize key concepts about collective capacities drawn from Lewis Mumford's critique of historical and modern sociotechnical arrangements. I investigate the possibility of accessing those capacities through improved design for Technology Assessment (TA), formal practices that engage experts and lay citizens in the evaluation of complex scientific and technical issues.

I analyze the components of Mumford's megamachine and align key concerns in two pivotal works that characterize the impact of collective capacities on society: Bruno Latour's Pasteurization of France (1988) and Elias Canetti's Crowds and Power (1962). As I create a model of collective capacities in the sociotechnical according to the parameters of Mumford's megamachine, I rehabilitate two established ideas about the behavior of crowds and about the undue influence of technological systems on human behavior. I depart from Mumford's tactics and those of Canetti and Latour and propose a novel focus for STS on "sociotechnical crowds" as a meaningful unit of social measure. I make clear that Mumford's critique of the sociotechnical status quo still informs the conditions for innovation today.

Using mixed mode qualitative methods in two types of empirical field studies, I then investigate how a focus on the characteristics and components of collective human capacities in sociotechnical systems can affect the design and performance of TA. I propose a new model of TA, Emergent Technology Assessment (ETA), which includes greater public participation and recognizes the interrelationship among experience, affect and the material in mediating the innovation process. The resulting model -- the "soft" megamachine --introduces new strategies to build capacity for responsible innovation in society.
ContributorsGano, Gretchen (Author) / Guston, David (Thesis advisor) / Miller, Clark (Thesis advisor) / Selin, Cynthia (Committee member) / Wetmore, Jameson (Committee member) / Arizona State University (Publisher)
Created2014