Matching Items (41)
Description
Thanks to continuous technology scaling, intelligent, fast and smaller digital systems are now available at affordable costs. As a result, digital systems have found use in a wide range of application areas that were not even imagined before, including medical (e.g., MRI, remote or post-operative monitoring devices, etc.), automotive (e.g., adaptive cruise control, anti-lock brakes, etc.), security systems (e.g., residential security gateways, surveillance devices, etc.), and in- and out-of-body sensing (e.g., capsule swallowed by patients measuring digestive system pH, heart monitors, etc.). Such computing systems, which are completely embedded within the application, are called embedded systems, as opposed to general purpose computing systems. In the design of such embedded systems, power consumption and reliability are indispensable system requirements. In battery operated portable devices, the battery is the single largest factor contributing to device cost, weight, recharging time, frequency and ultimately its usability. For example, in the Apple iPhone 4 smart-phone, the battery is $40\%$ of the device weight, occupies $36\%$ of its volume and allows only $7$ hours (over 3G) of talk time. As embedded systems find use in a range of sensitive applications, from bio-medical applications to safety and security systems, the reliability of the computations performed becomes a crucial factor. At our current technology-node, portable embedded systems are prone to expect failures due to soft errors at the rate of once-per-year; but with aggressive technology scaling, the rate is predicted to increase exponentially to once-per-hour. Over the years, researchers have been successful in developing techniques, implemented at different layers of the design-spectrum, to improve system power efficiency and reliability. Among the layers of design abstraction, I observe that the interface between the compiler and processor micro-architecture possesses a unique potential for efficient design optimizations. A compiler designer is able to observe and analyze the application software at a finer granularity; while the processor architect analyzes the system output (power, performance, etc.) for each executed instruction. At the compiler micro-architecture interface, if the system knowledge at the two design layers can be integrated, design optimizations at the two layers can be modified to efficiently utilize available resources and thereby achieve appreciable system-level benefits. To this effect, the thesis statement is that, ``by merging system design information at the compiler and micro-architecture design layers, smart compilers can be developed, that achieve reliable and power-efficient embedded computing through: i) Pure compiler techniques, ii) Hybrid compiler micro-architecture techniques, and iii) Compiler-aware architectures''. In this dissertation demonstrates, through contributions in each of the three compiler-based techniques, the effectiveness of smart compilers in achieving power-efficiency and reliability in embedded systems.
ContributorsJeyapaul, Reiley (Author) / Shrivastava, Aviral (Thesis advisor) / Vrudhula, Sarma (Committee member) / Clark, Lawrence (Committee member) / Colbourn, Charles (Committee member) / Arizona State University (Publisher)
Created2012
Description
For more than twenty years, clinical researchers have been publishing data regarding incidence and risk of adverse events (AEs) incurred during hospitalizations. Hospitals have standard operating policies and procedures (SOPP) to protect patients from AE. The AE specifics (rates, SOPP failures, timing and risk factors) during heart failure (HF) hospitalizations are unknown. There were 1,722 patients discharged with a primary diagnosis of HF from an academic hospital between January 2005 and December 2007. Three hundred eighty-one patients experienced 566 AEs, classified into four categories: medication (43.9%), infection (18.9%), patient care (26.3%), or procedural (10.9%). Three distinct analyses were performed: 1) patient's perspective of SOPP reliability including cumulative distribution and hazard functions of time to AEs; 2) Cox proportional hazards model to determine independent patient-specific risk factors for AEs; and 3) hospital administration's perspective of SOPP reliability through three years of the study including cumulative distribution and hazard functions of time between AEs and moving range statistical process control (SPC) charts for days between failures of each type. This is the first study, to our knowledge, to consider reliability of SOPP from both the patient's and hospital administration's perspective. AE rates in hospitalized patients are similar to other recently published reports and did not improve during the study period. Operations research methodologies will be necessary to improve reliability of care delivered to hospitalized patients.
ContributorsHuddleston, Jeanne (Author) / Fowler, John (Thesis advisor) / Montgomery, Douglas C. (Thesis advisor) / Gel, Esma (Committee member) / Shunk, Dan (Committee member) / Arizona State University (Publisher)
Created2012
Description
The Smart Grid initiative describes the collaborative effort to modernize the U.S. electric power infrastructure. Modernization efforts incorporate digital data and information technology to effectuate control, enhance reliability, encourage small customer sited distributed generation (DG), and better utilize assets. The Smart Grid environment is envisioned to include distributed generation, flexible and controllable loads, bidirectional communications using smart meters and other technologies. Sensory technology may be utilized as a tool that enhances operation including operation of the distribution system. Addressing this point, a distribution system state estimation algorithm is developed in this thesis. The state estimation algorithm developed here utilizes distribution system modeling techniques to calculate a vector of state variables for a given set of measurements. Measurements include active and reactive power flows, voltage and current magnitudes, phasor voltages with magnitude and angle information. The state estimator is envisioned as a tool embedded in distribution substation computers as part of distribution management systems (DMS); the estimator acts as a supervisory layer for a number of applications including automation (DA), energy management, control and switching. The distribution system state estimator is developed in full three-phase detail, and the effect of mutual coupling and single-phase laterals and loads on the solution is calculated. The network model comprises a full three-phase admittance matrix and a subset of equations that relates measurements to system states. Network equations and variables are represented in rectangular form. Thus a linear calculation procedure may be employed. When initialized to the vector of measured quantities and approximated non-metered load values, the calculation procedure is non-iterative. This dissertation presents background information used to develop the state estimation algorithm, considerations for distribution system modeling, and the formulation of the state estimator. Estimator performance for various power system test beds is investigated. Sample applications of the estimator to Smart Grid systems are presented. Applications include monitoring, enabling demand response (DR), voltage unbalance mitigation, and enhancing voltage control. Illustrations of these applications are shown. Also, examples of enhanced reliability and restoration using a sensory based automation infrastructure are shown.
ContributorsHaughton, Daniel Andrew (Author) / Heydt, Gerald T (Thesis advisor) / Vittal, Vijay (Committee member) / Ayyanar, Raja (Committee member) / Hedman, Kory W (Committee member) / Arizona State University (Publisher)
Created2012
Characterization and analysis of long term field aged photovoltaic modules and encapsulant materials
Description
Photovoltaic (PV) module degradation is a well-known issue, however understanding the mechanistic pathways in which modules degrade is still a major task for the PV industry. In order to study the mechanisms responsible for PV module degradation, the effects of these degradation mechanisms must be quantitatively measured to determine the severity of each degradation mode. In this thesis multiple modules from three climate zones (Arizona, California and Colorado) were investigated for a single module glass/polymer construction (Siemens M55) to determine the degree to which they had degraded, and the main factors that contributed to that degradation. To explain the loss in power, various nondestructive and destructive techniques were used to indicate possible causes of loss in performance. This is a two-part thesis. Part 1 presents non-destructive test results and analysis and Part 2 presents destructive test results and analysis.
ContributorsChicca, Matthew (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Rogers, Bradley (Committee member) / Srinivasan, Devarajan (Committee member) / Arizona State University (Publisher)
Created2015
Description
Thin-film modules of all technologies often suffer from performance degradation over time. Some of the performance changes are reversible and some are not, which makes deployment, testing, and energy-yield prediction more challenging. The most commonly alleged causes of instability in CdTe device, such as “migration of Cu,” have been investigated rigorously over the past fifteen years. As all defects, intrinsic or extrinsic, interact with the electrical potential and free carriers so that charged defects may drift in the electric field and changing ionization state with excess free carriers. Such complexity of interactions in CdTe makes understanding of temporal changes in device performance even more challenging. The goal of the work in this dissertation is, thus, to eliminate the ambiguity between the observed performance changes under stress and their physical root cause by enabling a depth of modeling that takes account of diffusion and drift at the atomistic level coupled to the electronic subsystem responsible for a PV device’s function. The 1D Unified Solver, developed as part of this effort, enables us to analyze PV devices at a greater depth.
In this dissertation, the implementation of a drift-diffusion model defect migration simulator, development of an implicit reaction scheme for total mass conservation, and a couple of other numerical schemes to improve the overall flexibility and robustness of this coupled Unified Solver is discussed. Preliminary results on Cu (with or without Cl-treatment) annealing simulations in both single-crystal CdTe wafer and poly-crystalline CdTe devices show promising agreement to experimental findings, providing a new perspective in the research of improving doping concentration hence the open-circuit voltage of CdTe technology. Furthermore, on the reliability side, in agreement of previous experimental reports, simulation results suggest possibility of Cu depletion in short-circuited cells stressed at elevated temperature. The developed solver also successfully demonstrated that mobile donor migration can be used to explain solar cell performance changes under different stress conditions.
In this dissertation, the implementation of a drift-diffusion model defect migration simulator, development of an implicit reaction scheme for total mass conservation, and a couple of other numerical schemes to improve the overall flexibility and robustness of this coupled Unified Solver is discussed. Preliminary results on Cu (with or without Cl-treatment) annealing simulations in both single-crystal CdTe wafer and poly-crystalline CdTe devices show promising agreement to experimental findings, providing a new perspective in the research of improving doping concentration hence the open-circuit voltage of CdTe technology. Furthermore, on the reliability side, in agreement of previous experimental reports, simulation results suggest possibility of Cu depletion in short-circuited cells stressed at elevated temperature. The developed solver also successfully demonstrated that mobile donor migration can be used to explain solar cell performance changes under different stress conditions.
ContributorsGuo, Da (Author) / Vasileska, Dragica (Thesis advisor) / Sankin, Igor (Committee member) / Goodnick, Stephen (Committee member) / Bertoni, Mariana (Committee member) / Arizona State University (Publisher)
Created2017
Description
The aging mechanism in devices is prone to uncertainties due to dynamic stress conditions. In AMS circuits these can lead to momentary fluctuations in circuit voltage that may be missed by a compact model and hence cause unpredictable failure. Firstly, multiple aging effects in the devices may have underlying correlations. The generation of new traps during TDDB may significantly accelerate BTI, since these traps are close to the dielectric-Si interface in scaled technology. Secondly, the prevalent reliability analysis lacks a direct validation of the lifetime of devices and circuits. The aging mechanism of BTI causes gradual degradation of the device leading to threshold voltage shift and increasing the failure rate. In the 28nm HKMG technology, contribution of BTI to NMOS degradation has become significant at high temperature as compared to Channel Hot Carrier (CHC). This requires revising the End of Lifetime (EOL) calculation based on contribution from induvial aging effects especially in feedback loops. Conventionally, aging in devices is extrapolated from a short-term measurement, but this practice results in unreliable prediction of EOL caused by variability in initial parameters and stress conditions. To mitigate the extrapolation issues and improve predictability, this work aims at providing a new approach to test the device to EOL in a fast and controllable manner. The contributions of this thesis include: (1) based on stochastic trapping/de-trapping mechanism, new compact BTI models are developed and verified with 14nm FinFET and 28nm HKMG data. Moreover, these models are implemented into circuit simulation, illustrating a significant increase in failure rate due to accelerated BTI, (2) developing a model to predict accelerated aging under special conditions like feedback loops and stacked inverters, (3) introducing a feedback loop based test methodology called Adaptive Accelerated Aging (AAA) that can generate accurate aging data till EOL, (4) presenting simulation and experimental data for the models and providing test setup for multiple stress conditions, including those for achieving EOL in 1 hour device as well as ring oscillator (RO) circuit for validation of the proposed methodology, and (5) scaling these models for finding a guard band for VLSI design circuits that can provide realistic aging impact.
ContributorsPatra, Devyani (Author) / Cao, Yu (Thesis advisor) / Barnaby, Hugh (Thesis advisor) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2017
Description
In this work, an advanced simulation study of reliability in millimeter-wave (mm-wave) GaN Devices for power amplifier (PA) applications is performed by means of a particle-based full band Cellular Monte Carlo device simulator (CMC). The goal of the study is to obtain a systematic characterization of the performance of GaN devices operating in DC, small signal AC and large-signal radio-frequency (RF) conditions emphasizing on the microscopic properties that correlate to degradation of device performance such as generation of hot carriers, presence of material defects and self-heating effects. First, a review of concepts concerning GaN technology, devices, reliability mechanisms and PA design is presented in chapter 2. Then, in chapter 3 a study of non-idealities of AlGaN/GaN heterojunction diodes is performed, demonstrating that mole fraction variations and the presence of unintentional Schottky contacts are the main limiting factor for high current drive of the devices under study. Chapter 4 consists in a study of hot electron generation in GaN HEMTs, in terms of the accurate simulation of the electron energy distribution function (EDF) obtained under DC and RF operation, taking into account frequency and temperature variations. The calculated EDFs suggest that Class AB PAs operating at low frequency (10 GHz) are more robust to hot carrier effects than when operating under DC or high frequency RF (up to 40 GHz). Also, operation under Class A yields higher EDFs than Class AB indicating lower reliability. This study is followed in chapter 5 by the proposal of a novel π-Shaped gate contact for GaN HEMTs which effectively reduces the hot electron generation while preserving device performance. Finally, in chapter 6 the electro-thermal characterization of GaN-on-Si HEMTs is performed by means of an expanded CMC framework, where charge and heat transport are self-consistently coupled. After the electro-thermal model is validated to experimental data, the assessment of self-heating under lateral scaling is considered.
ContributorsLatorre Rey, Alvaro Daniel (Author) / Saraniti, Marco (Thesis advisor) / Kitchen, Jennifer (Committee member) / Goodnick, Stephen M (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2018
Description
Advances in semiconductor technology have brought computer-based systems intovirtually all aspects of human life. This unprecedented integration of semiconductor based systems in our lives has significantly increased the domain and the number
of safety-critical applications – application with unacceptable consequences of failure. Software-level error resilience schemes are attractive because they can provide commercial-off-the-shelf microprocessors with adaptive and scalable reliability.
Among all software-level error resilience solutions, in-application instruction replication based approaches have been widely used and are deemed to be the most effective. However, existing instruction-based replication schemes only protect some part of computations i.e. arithmetic and logical instructions and leave the rest as unprotected. To improve the efficacy of instruction-level redundancy-based approaches, we developed several error detection and error correction schemes. nZDC (near Zero silent
Data Corruption) is an instruction duplication scheme which protects the execution of whole application. Rather than detecting errors on register operands of memory and control flow operations, nZDC checks the results of such operations. nZDC en
sures the correct execution of memory write instruction by reloading stored value and checking it against redundantly computed value. nZDC also introduces a novel control flow checking mechanism which replicates compare and branch instructions and
detects both wrong direction branches as well as unwanted jumps. Fault injection experiments show that nZDC can improve the error coverage of the state-of-the-art schemes by more than 10x, without incurring any more performance penalty. Further
more, we introduced two error recovery solutions. InCheck is our backward recovery solution which makes light-weighted error-free checkpoints at the basic block granularity. In the case of error, InCheck reverts the program execution to the beginning of last executed basic block and resumes the execution by the aid of preserved in formation. NEMESIS is our forward recovery scheme which runs three versions of computation and detects errors by checking the results of all memory write and branch
operations. In the case of a mismatch, NEMESIS diagnosis routine decides if the error is recoverable. If yes, NEMESIS recovery routine reverts the effect of error from the program state and resumes program normal execution from the error detection
point.
of safety-critical applications – application with unacceptable consequences of failure. Software-level error resilience schemes are attractive because they can provide commercial-off-the-shelf microprocessors with adaptive and scalable reliability.
Among all software-level error resilience solutions, in-application instruction replication based approaches have been widely used and are deemed to be the most effective. However, existing instruction-based replication schemes only protect some part of computations i.e. arithmetic and logical instructions and leave the rest as unprotected. To improve the efficacy of instruction-level redundancy-based approaches, we developed several error detection and error correction schemes. nZDC (near Zero silent
Data Corruption) is an instruction duplication scheme which protects the execution of whole application. Rather than detecting errors on register operands of memory and control flow operations, nZDC checks the results of such operations. nZDC en
sures the correct execution of memory write instruction by reloading stored value and checking it against redundantly computed value. nZDC also introduces a novel control flow checking mechanism which replicates compare and branch instructions and
detects both wrong direction branches as well as unwanted jumps. Fault injection experiments show that nZDC can improve the error coverage of the state-of-the-art schemes by more than 10x, without incurring any more performance penalty. Further
more, we introduced two error recovery solutions. InCheck is our backward recovery solution which makes light-weighted error-free checkpoints at the basic block granularity. In the case of error, InCheck reverts the program execution to the beginning of last executed basic block and resumes the execution by the aid of preserved in formation. NEMESIS is our forward recovery scheme which runs three versions of computation and detects errors by checking the results of all memory write and branch
operations. In the case of a mismatch, NEMESIS diagnosis routine decides if the error is recoverable. If yes, NEMESIS recovery routine reverts the effect of error from the program state and resumes program normal execution from the error detection
point.
ContributorsDidehban, Moslem (Author) / Shrivastava, Aviral (Thesis advisor) / Wu, Carole-Jean (Committee member) / Clark, Lawrence (Committee member) / Mahlke, Scott (Committee member) / Arizona State University (Publisher)
Created2018
Description
The present research expands on prior research that demonstrated a prototypical facial expression in response to cute, baby-like Kindchenschema targets. This expression, referred to as the tenderness expression, is recognizable to onlookers as a response to such stimuli. Across two studies, the current research examined if there were differences in perceptions of trustworthiness (Studies 1 and 2) and willingness to trust (Study 2) toward individuals displaying the tenderness expression as compared to a Duchenne smile or a neutral expression. Results indicate the tenderness expression is associated with lower ratings of trustworthiness relative to a smile, but no differences among the expressions on willingness to trust. Exploratory analyses demonstrate a replicated pattern of differences on the Big Five Personality Inventory among these three expressions. While these findings were not consistent with a priori hypotheses, this research provides further insight into the social implications associated with this tenderness expression.
ContributorsO'Neil, Makenzie J (Author) / Shiota, Michelle N. (Thesis advisor) / Kenrick, Douglas T. (Committee member) / Wynne, Clive D.L. (Committee member) / Bradley, Robert H. (Committee member) / Arizona State University (Publisher)
Created2019
Description
The Resistive Random Access Memory (ReRAM) is an emerging non-volatile memory
technology because of its attractive attributes, including excellent scalability (< 10 nm), low
programming voltage (< 3 V), fast switching speed (< 10 ns), high OFF/ON ratio (> 10),
good endurance (up to 1012 cycles) and great compatibility with silicon CMOS technology [1].
However, ReRAM suffers from larger write latency, energy and reliability issue compared to
Dynamic Random Access Memory (DRAM). To improve the energy-efficiency, latency efficiency and reliability of ReRAM storage systems, a low cost cross-layer approach that spans device, circuit, architecture and system levels is proposed.
For 1T1R 2D ReRAM system, the effect of both retention and endurance errors on
ReRAM reliability is considered. Proposed approach is to design circuit-level and architecture-level techniques to reduce raw Bit Error Rate significantly and then employ low cost Error Control Coding to achieve the desired lifetime.
For 1S1R 2D ReRAM system, a cross-point array with “multi-bit per access” per subarray
is designed for high energy-efficiency and good reliability. The errors due to cell-level as well
as array-level variations are analyzed and a low cost scheme to maintain reliability and latency
with low energy consumption is proposed.
For 1S1R 3D ReRAM system, access schemes which activate multiple subarrays with
multiple layers in a subarray are used to achieve high energy efficiency through activating fewer
subarray, and good reliability is achieved through innovative data organization.
Finally, a novel ReRAM-based accelerator design is proposed to support multiple
Convolutional Neural Networks (CNN) topologies including VGGNet, AlexNet and ResNet.
The multi-tiled architecture consists of 9 processing elements per tile, where each tile
implements the dot product operation using ReRAM as computation unit. The processing
elements operate in a systolic fashion, thereby maximizing input feature map reuse and
minimizing interconnection cost. The system-level evaluation on several network benchmarks
show that the proposed architecture can improve computation efficiency and energy efficiency
compared to a state-of-the-art ReRAM-based accelerator.
technology because of its attractive attributes, including excellent scalability (< 10 nm), low
programming voltage (< 3 V), fast switching speed (< 10 ns), high OFF/ON ratio (> 10),
good endurance (up to 1012 cycles) and great compatibility with silicon CMOS technology [1].
However, ReRAM suffers from larger write latency, energy and reliability issue compared to
Dynamic Random Access Memory (DRAM). To improve the energy-efficiency, latency efficiency and reliability of ReRAM storage systems, a low cost cross-layer approach that spans device, circuit, architecture and system levels is proposed.
For 1T1R 2D ReRAM system, the effect of both retention and endurance errors on
ReRAM reliability is considered. Proposed approach is to design circuit-level and architecture-level techniques to reduce raw Bit Error Rate significantly and then employ low cost Error Control Coding to achieve the desired lifetime.
For 1S1R 2D ReRAM system, a cross-point array with “multi-bit per access” per subarray
is designed for high energy-efficiency and good reliability. The errors due to cell-level as well
as array-level variations are analyzed and a low cost scheme to maintain reliability and latency
with low energy consumption is proposed.
For 1S1R 3D ReRAM system, access schemes which activate multiple subarrays with
multiple layers in a subarray are used to achieve high energy efficiency through activating fewer
subarray, and good reliability is achieved through innovative data organization.
Finally, a novel ReRAM-based accelerator design is proposed to support multiple
Convolutional Neural Networks (CNN) topologies including VGGNet, AlexNet and ResNet.
The multi-tiled architecture consists of 9 processing elements per tile, where each tile
implements the dot product operation using ReRAM as computation unit. The processing
elements operate in a systolic fashion, thereby maximizing input feature map reuse and
minimizing interconnection cost. The system-level evaluation on several network benchmarks
show that the proposed architecture can improve computation efficiency and energy efficiency
compared to a state-of-the-art ReRAM-based accelerator.
ContributorsMao, Manqing (Author) / Chakrabariti, Chaitali (Thesis advisor) / Yu, Shimeng (Committee member) / Cao, Yu (Committee member) / Orgas, Umit (Committee member) / Arizona State University (Publisher)
Created2019