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In very small electronic devices the alternate capture and emission of carriers at an individual defect site located at the interface of Si:SiO2 of a MOSFET generates discrete switching in the device conductance referred to as a random telegraph signal (RTS) or random telegraph noise (RTN). In this research work,

In very small electronic devices the alternate capture and emission of carriers at an individual defect site located at the interface of Si:SiO2 of a MOSFET generates discrete switching in the device conductance referred to as a random telegraph signal (RTS) or random telegraph noise (RTN). In this research work, the integration of random defects positioned across the channel at the Si:SiO2 interface from source end to the drain end in the presence of different random dopant distributions are used to conduct Ensemble Monte-Carlo ( EMC ) based numerical simulation of key device performance metrics for 45 nm gate length MOSFET device. The two main performance parameters that affect RTS based reliability measurements are percentage change in threshold voltage and percentage change in drain current fluctuation in the saturation region. It has been observed as a result of the simulation that changes in both and values moderately decrease as the defect position is gradually moved from source end to the drain end of the channel. Precise analytical device physics based model needs to be developed to explain and assess the EMC simulation based higher VT fluctuations as experienced for trap positions at the source side. A new analytical model has been developed that simultaneously takes account of dopant number variations in the channel and depletion region underneath and carrier mobility fluctuations resulting from fluctuations in surface potential barriers. Comparisons of this new analytical model along with existing analytical models are shown to correlate with 3D EMC simulation based model for assessment of VT fluctuations percentage induced by a single interface trap. With scaling of devices beyond 32 nm node, halo doping at the source and drain are routinely incorporated to combat the threshold voltage roll-off that takes place with effective channel length reduction. As a final study on this regard, 3D EMC simulation method based computations of threshold voltage fluctuations have been performed for varying source and drain halo pocket length to illustrate the threshold voltage fluctuations related reliability problems that have been aggravated by trap positions near the source at the interface compared to conventional 45 nm MOSFET.
ContributorsAshraf, Nabil Shovon (Author) / Vasileska, Dragica (Thesis advisor) / Schroder, Dieter (Committee member) / Goodnick, Stephen (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
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Description
ABSTRACT An Ensemble Monte Carlo (EMC) computer code has been developed to simulate, semi-classically, spin-dependent electron transport in quasi two-dimensional (2D) III-V semiconductors. The code accounts for both three-dimensional (3D) and quasi-2D transport, utilizing either 3D or 2D scattering mechanisms, as appropriate. Phonon, alloy, interface roughness, and impurity scattering mechanisms

ABSTRACT An Ensemble Monte Carlo (EMC) computer code has been developed to simulate, semi-classically, spin-dependent electron transport in quasi two-dimensional (2D) III-V semiconductors. The code accounts for both three-dimensional (3D) and quasi-2D transport, utilizing either 3D or 2D scattering mechanisms, as appropriate. Phonon, alloy, interface roughness, and impurity scattering mechanisms are included, accounting for the Pauli Exclusion Principle via a rejection algorithm. The 2D carrier states are calculated via a self-consistent 1D Schrödinger-3D-Poisson solution in which the charge distribution of the 2D carriers in the quantization direction is taken as the spatial distribution of the squared envelope functions within the Hartree approximation. The wavefunctions, subband energies, and 2D scattering rates are updated periodically by solving a series of 1D Schrödinger wave equations (SWE) over the real-space domain of the device at fixed time intervals. The electrostatic potential is updated by periodically solving the 3D Poisson equation. Spin-polarized transport is modeled via a spin density-matrix formalism that accounts for D'yakanov-Perel (DP) scattering. Also, the code allows for the easy inclusion of additional scattering mechanisms and structural modifications to devices. As an application of the simulator, the current voltage characteristics of an InGaAs/InAlAs HEMT are simulated, corresponding to nanoscale III-V HEMTs currently being fabricated by Intel Corporation. The comparative effects of various scattering parameters, material properties and structural attributes are investigated and compared with experiments where reasonable agreement is obtained. The spatial evolution of spin-polarized carriers in prototypical Spin Field Effect Transistor (SpinFET) devices is then simulated. Studies of the spin coherence times in quasi-2D structures is first investigated and compared to experimental results. It is found that the simulated spin coherence times for GaAs structures are in reasonable agreement with experiment. The SpinFET structure studied is a scaled-down version of the InGaAs/InAlAs HEMT discussed in this work, in which spin-polarized carriers are injected at the source, and the coherence length is studied as a function of gate voltage via the Rashba effect.
ContributorsTierney, Brian David (Author) / Goodnick, Stephen (Thesis advisor) / Ferry, David (Committee member) / Akis, Richard (Committee member) / Saraniti, Marco (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2011
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Description
In this work, transport in nanowire materials and nanowire field effect transistors is studied using a full band Monte Carlo simulator within the tight binding basis. Chapter 1 is dedicated to the importance of nanowires and nanoscale devices in present day electronics and the necessity to use a computationally efficient

In this work, transport in nanowire materials and nanowire field effect transistors is studied using a full band Monte Carlo simulator within the tight binding basis. Chapter 1 is dedicated to the importance of nanowires and nanoscale devices in present day electronics and the necessity to use a computationally efficient tool to simulate transport in these devices. Chapter 2 discusses the calculation of the full band structure of nanowires based on an atomistic tight binding approach, particularly noting the use of the exact same tight binding parameters for bulk band structures as well as the nanowire band structures. Chapter 3 contains the scattering rate formula for deformation potential, polar optical phonon, ionized impurity and impact ionization scattering in nanowires using Fermi’s golden rule and the tight binding basis to describe the wave functions. A method to calculate the dielectric screening in 1D systems within the tight binding basis is also described. Importantly, the scattering rates of nanowires tends to the bulk scattering rates at high energies, enabling the use of the same parameter set that were fitted to bulk experimental data to be used in the simulation of nanowire transport. A robust and efficient method to model interband tunneling is discussed in chapter 4 and its importance in nanowire transport is highlighted. In chapter 5, energy relaxation of excited electrons is studied for free standing nanowires and cladded nanowires. Finally, in chapter 6, a full band Monte Carlo particle based solver is created which treats confinement in a full quantum way and the current voltage characteristics as well as the subthreshold swing and percentage of ballistic transport is analyzed for an In0.7Ga0.3As junctionless nanowire field effect transistor.
ContributorsHathwar, Raghuraj (Author) / Goodnick, Stephen M (Committee member) / Saraniti, Marco (Committee member) / Vasileska, Dragica (Committee member) / Ferry, David K. (Committee member) / Arizona State University (Publisher)
Created2016
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Description
4H-SiC has been widely used in many applications. All of these benefit from its extremely high critical electric field and good electron mobility. For example, 4H-SiC possesses a critical field ten times higher than that of Si, which allows high-voltage blocking layers composed of 4H-SiC to be approximately a tenth

4H-SiC has been widely used in many applications. All of these benefit from its extremely high critical electric field and good electron mobility. For example, 4H-SiC possesses a critical field ten times higher than that of Si, which allows high-voltage blocking layers composed of 4H-SiC to be approximately a tenth the thickness of a comparable Si device. This, in turn, reduces the device on-resistance and power losses while maintaining the same high blocking capability.

Unfortunately, commercial TCAD tools like Sentaurus and Silvaco Atlas are based on the effective mass approximation, while most 4H-SiC devices are not operated under low electric field, so the parabolic-like band approximation does not hold anymore. Hence, to get more accurate and reliable simulation results, full-band analysis is needed. The first step in the development of a full-band device simulator is the calculation of the band structure. In this work, the empirical pseudopotential method (EPM) is adopted. The next task in the sequence is the calculation of the scattering rates. Acoustic, non-polar optical phonon, polar optical phonon and Coulomb scattering are considered. Coulomb scattering is treated in real space using the particle-particle-particle-mesh (P3M) approach. The third task is coupling the bulk full-band solver with a 3D Poisson equation solver to generate a full-band device simulator.

For proof-of-concept of the methodology adopted here, a 3D resistor is simulated first. From the resistor simulations, the low-field electron mobility dependence upon Coulomb scattering in 4H-SiC devices is extracted. The simulated mobility results agree very well with available experimental data. Next, a 3D VDMOS is simulated. The nature of the physical processes occurring in both steady-state and transient conditions are revealed for the two generations of 3D VDMOS devices being considered in the study.

Due to its comprehensive nature, the developed tool serves as a basis for future investigation of 4H-SiC power devices.
ContributorsCheng, Chi-Yin (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen M (Thesis advisor) / Ponce, Fernando (Committee member) / Zhao, Yuji (Committee member) / Arizona State University (Publisher)
Created2020