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- All Subjects: Semiconductors--Characterization.
- Genre: Doctoral Dissertation
- Creators: Goryll, Michael
Description
The first part describes Metal Semiconductor Field Effect Transistor (MESFET) based fundamental analog building blocks designed and fabricated in a single poly, 3-layer metal digital CMOS technology utilizing fully depletion mode MESFET devices. DC characteristics were measured by varying the power supply from 2.5V to 5.5V. The measured DC transfer curves of amplifiers show good agreement with the simulated ones with extracted models from the same process. The accuracy of the current mirror showing inverse operation is within ±15% for the current from 0 to 1.5mA with the power supply from 2.5 to 5.5V. The second part presents a low-power image recognition system with a novel MESFET device fabricated on a CMOS substrate. An analog image recognition system with power consumption of 2.4mW/cell and a response time of 6µs is designed, fabricated and characterized. The experimental results verified the accuracy of the extracted SPICE model of SOS MESFETs. The response times of 4µs and 6µs for one by four and one by eight arrays, respectively, are achieved with the line recognition. Each core cell for both arrays consumes only 2.4mW. The last part presents a CMOS low-power transceiver in MICS band is presented. The LNA core has an integrated mixer in a folded configuration. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. The SRO is used in a wakeup RX for the wake-up signal reception. The all digital frequency-locked loop drives a class AB power amplifier in a transmitter. The sensitivity of -85dBm in the wakeup RX is achieved with the power consumption of 320µW and 400µW at the data rates of 100kb/s and 200kb/s from 1.8V, respectively. The sensitivities of -70dBm and -98dBm in the data-link RX are achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600µW and 1.5mW at 1.2V and 1.8V, respectively.
ContributorsKim, Sung (Author) / Bakkaloglu, Bertan (Thesis advisor) / Christen, Jennifer Blain (Committee member) / Cao, Yu (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2011
Description
InAs/InAsSb type-II superlattices (T2SLs) can be considered as potential alternatives for conventional HgCdTe photodetectors due to improved uniformity, lower manufacturing costs with larger substrates, and possibly better device performance. This dissertation presents a comprehensive study on the structural, optical and electrical properties of InAs/InAsSb T2SLs grown by Molecular Beam Epitaxy.
The effects of different growth conditions on the structural quality were thoroughly investigated. Lattice-matched condition was successfully achieved and material of exceptional quality was demonstrated.
After growth optimization had been achieved, structural defects could hardly be detected, so different characterization techniques, including etch-pit-density (EPD) measurements, cathodoluminescence (CL) imaging and X-ray topography (XRT), were explored, in attempting to gain better knowledge of the sparsely distributed defects. EPD revealed the distribution of dislocation-associated pits across the wafer. Unfortunately, the lack of contrast in images obtained by CL imaging and XRT indicated their inability to provide any quantitative information about defect density in these InAs/InAsSb T2SLs.
The nBn photodetectors based on mid-wave infrared (MWIR) and long-wave infrared (LWIR) InAs/InAsSb T2SLs were fabricated. The significant difference in Ga composition in the barrier layer coupled with different dark current behavior, suggested the possibility of different types of band alignment between the barrier layers and the absorbers. A positive charge density of 1.8 × 1017/cm3 in the barrier of MWIR nBn photodetector, as determined by electron holography, confirmed the presence of a potential well in its valence band, thus identifying type-II alignment. In contrast, the LWIR nBn photodetector was shown to have type-I alignment because no sign of positive charge was detected in its barrier.
Capacitance-voltage measurements were performed to investigate the temperature dependence of carrier densities in a metal-oxide-semiconductor (MOS) structure based on MWIR InAs/InAsSb T2SLs, and a nBn structure based on LWIR InAs/InAsSb T2SLs. No carrier freeze-out was observed in either sample, indicating very shallow donor levels. The decrease in carrier density when temperature increased was attributed to the increased density of holes that had been thermally excited from localized states near the oxide/semiconductor interface in the MOS sample. No deep-level traps were revealed in deep-level transient spectroscopy temperature scans.
The effects of different growth conditions on the structural quality were thoroughly investigated. Lattice-matched condition was successfully achieved and material of exceptional quality was demonstrated.
After growth optimization had been achieved, structural defects could hardly be detected, so different characterization techniques, including etch-pit-density (EPD) measurements, cathodoluminescence (CL) imaging and X-ray topography (XRT), were explored, in attempting to gain better knowledge of the sparsely distributed defects. EPD revealed the distribution of dislocation-associated pits across the wafer. Unfortunately, the lack of contrast in images obtained by CL imaging and XRT indicated their inability to provide any quantitative information about defect density in these InAs/InAsSb T2SLs.
The nBn photodetectors based on mid-wave infrared (MWIR) and long-wave infrared (LWIR) InAs/InAsSb T2SLs were fabricated. The significant difference in Ga composition in the barrier layer coupled with different dark current behavior, suggested the possibility of different types of band alignment between the barrier layers and the absorbers. A positive charge density of 1.8 × 1017/cm3 in the barrier of MWIR nBn photodetector, as determined by electron holography, confirmed the presence of a potential well in its valence band, thus identifying type-II alignment. In contrast, the LWIR nBn photodetector was shown to have type-I alignment because no sign of positive charge was detected in its barrier.
Capacitance-voltage measurements were performed to investigate the temperature dependence of carrier densities in a metal-oxide-semiconductor (MOS) structure based on MWIR InAs/InAsSb T2SLs, and a nBn structure based on LWIR InAs/InAsSb T2SLs. No carrier freeze-out was observed in either sample, indicating very shallow donor levels. The decrease in carrier density when temperature increased was attributed to the increased density of holes that had been thermally excited from localized states near the oxide/semiconductor interface in the MOS sample. No deep-level traps were revealed in deep-level transient spectroscopy temperature scans.
ContributorsShen, Xiaomeng (Author) / Zhang, Yong-Hang (Thesis advisor) / Smith, David J. (Thesis advisor) / Alford, Terry (Committee member) / Goryll, Michael (Committee member) / Mccartney, Martha R (Committee member) / Arizona State University (Publisher)
Created2015
Description
Semiconductor manufacturing economics necessitate the development of innovative device measurement techniques for quick assessment of products. Several novel electrical measurement techniques will be proposed for screening silicon device parameters. The studied parameters range from oxide reliability, and carrier lifetime in MOS capacitors to the power MOSFET reverse recovery.
It will be shown that positive charge trapping is a dominant process when thick oxides are stressed through the ramped voltage test (RVT). Exploiting the physics behind positive charge generation/trapping at high electric fields, a fast I-V measurement technique is proposed that can be used to effectively distinguish the ultra-thick oxides' intrinsic quality at low electric fields.
Next, two novel techniques will be presented for studying the carrier lifetime in MOS Capacitor devices. It will be shown that the deep-level transient spectroscopy (DLTS) can be applied to MOS test structures as a swift mean for screening the generation lifetime. Recombination lifetime will also be addressed by introducing the optically-excited MOS technique as a promising tool.
The last part of this work is devoted to the reverse recovery behavior of the body diode of power MOSFETs. The correct interpretation of the LDMOS reverse recovery is challenging and requires special attention. A simple approach will be presented to extract meaningful lifetime values from the reverse recovery of LDMOS body-diodes exploiting their gate voltage and the magnitude of the reverse bias.
It will be shown that positive charge trapping is a dominant process when thick oxides are stressed through the ramped voltage test (RVT). Exploiting the physics behind positive charge generation/trapping at high electric fields, a fast I-V measurement technique is proposed that can be used to effectively distinguish the ultra-thick oxides' intrinsic quality at low electric fields.
Next, two novel techniques will be presented for studying the carrier lifetime in MOS Capacitor devices. It will be shown that the deep-level transient spectroscopy (DLTS) can be applied to MOS test structures as a swift mean for screening the generation lifetime. Recombination lifetime will also be addressed by introducing the optically-excited MOS technique as a promising tool.
The last part of this work is devoted to the reverse recovery behavior of the body diode of power MOSFETs. The correct interpretation of the LDMOS reverse recovery is challenging and requires special attention. A simple approach will be presented to extract meaningful lifetime values from the reverse recovery of LDMOS body-diodes exploiting their gate voltage and the magnitude of the reverse bias.
ContributorsElhami Khorasani, Arash (Author) / Alford, Terry L. (Thesis advisor) / Goryll, Michael (Committee member) / Theodore, David (Committee member) / Arizona State University (Publisher)
Created2015