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Semiconductor nanowires are featured by their unique one-dimensional structure which makes them promising for small scale electronic and photonic device applications. Among them, III-V material nanowires are particularly outstanding due to their good electronic properties. In bulk, these materials reveal electron mobility much higher than conventional silicon based devices, for

Semiconductor nanowires are featured by their unique one-dimensional structure which makes them promising for small scale electronic and photonic device applications. Among them, III-V material nanowires are particularly outstanding due to their good electronic properties. In bulk, these materials reveal electron mobility much higher than conventional silicon based devices, for example at room temperature, InAs field effect transistor (FET) has electron mobility of 40,000 cm2/Vs more than 10 times of Si FET. This makes such materials promising for high speed nanowire FETs. With small bandgap, such as 0.354 eV for InAs and 1.52 eV for GaAs, it does not need high voltage to turn on such devices which leads to low power consumption devices. Another feature of direct bandgap allows their applications of optoelectronic devices such as avalanche photodiodes. However, there are challenges to face up. Due to their large surface to volume ratio, nanowire devices typically are strongly affected by the surface states. Although nanowires can be grown into single crystal structure, people observe crystal defects along the wires which can significantly affect the performance of devices. In this work, FETs made of two types of III-V nanowire, GaAs and InAs, are demonstrated. These nanowires are grown by catalyst-free MOCVD growth method. Vertically nanowires are transferred onto patterned substrates for coordinate calibration. Then electrodes are defined by e-beam lithography followed by deposition of contact metals. Prior to metal deposition, however, the substrates are dipped in ammonium hydroxide solution to remove native oxide layer formed on nanowire surface. Current vs. source-drain voltage with different gate bias are measured at room temperature. GaAs nanowire FETs show photo response while InAs nanowire FETs do not show that. Surface passivation is performed on GaAs FETs by using ammonium surfide solution. The best results on current increase is observed with around 20-30 minutes chemical treatment time. Gate response measurements are performed at room temperature, from which field effect mobility as high as 1490 cm2/Vs is extracted for InAs FETs. One major contributor for this is stacking faults defect existing along nanowires. For InAs FETs, thermal excitations observed from temperature dependent results which leads us to investigate potential barriers.
ContributorsLiang, Hanshuang (Author) / Yu, Hongbin (Thesis advisor) / Ferry, David (Committee member) / Tracy, Clarence (Committee member) / Arizona State University (Publisher)
Created2011
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Description
Moore's law has been the most important driving force for the tremendous progress of semiconductor industry. With time the transistors which form the fundamental building block of any integrated circuit have been shrinking in size leading to smaller and faster electronic devices.As the devices scale down thermal effects and

Moore's law has been the most important driving force for the tremendous progress of semiconductor industry. With time the transistors which form the fundamental building block of any integrated circuit have been shrinking in size leading to smaller and faster electronic devices.As the devices scale down thermal effects and the short channel effects become the important deciding factors in determining transistor architecture.SOI (Silicon on Insulator) devices have been excellent alternative to planar MOSFET for ultimate CMOS scaling since they mitigate short channel effects. Hence as a part of thesis we tried to study the benefits of the SOI technology especially for lower technology nodes when the channel thickness reduces down to sub 10nm regime. This work tries to explore the effects of structural confinement due to reduced channel thickness on the electrostatic behavior of DG SOI MOSFET. DG SOI MOSFET form the Qfinfet which is an alternative to existing Finfet structure. Qfinfet was proposed and patented by the Finscale Inc for sub 10nm technology nodes.

As part of MS Thesis we developed electrostatic simulator for DG SOI devices by implementing the self consistent full band Schrodinger Poisson solver. We used the Empirical Pseudopotential method in conjunction with supercell approach to solve the Schrodinger Equation. EPM was chosen because it has few empirical parameters which give us good accuracy for experimental results. Also EPM is computationally less expensive as compared to the atomistic methods like DFT(Density functional theory) and NEGF (Non-equilibrium Green's function). In our workwe considered two crystallographic orientations of Si,namely [100] and [110].
ContributorsLaturia, Akash (Author) / Vasileska, Dragica (Thesis advisor) / Ferry, David (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2016