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- Creators: Yu, Hongbin
- Creators: Ferry, David K.
Description
Semiconductor devices are generally analyzed with relatively simple equations or with detailed computer simulations. Most text-books use these simple equations and show device diagrams that are frequently very simplified and occasionally incorrect. For example, the carrier densities near the pinch-off point in MOSFETs and JFETs and the minority carrier density in the base near the reverse-biased base-collector junction are frequently assumed to be zero or near zero. Also the channel thickness at the pinch-off point is often shown to approach zero. None of these assumptions can be correct. The research in thesis addresses these points. I simulated the carrier densities, potentials, electric fields etc. of MOSFETs, BJTs and JFETs at and near the pinch-off regions to determine exactly what happens there. I also simulated the behavior of the quasi-Fermi levels. For MOSFETs, the channel thickness expands slightly before the pinch-off point and then spreads out quickly in a triangular shape and the space-charge region under the channel actually shrinks as the potential increases from source to drain. For BJTs, with collector-base junction reverse biased, most minority carriers diffuse through the base from emitter to collector very fast, but the minority carrier concentration at the collector-base space-charge region is not zero. For JFETs, the boundaries of the space-charge region are difficult to determine, the channel does not disappear after pinch off, the shape of channel is always tapered, and the carrier concentration in the channel decreases progressively. After simulating traditional sized devices, I also simulated typical nano-scaled devices and show that they behave similarly to large devices. These simulation results provide a more complete understanding of device physics and device operation in those regions usually not addressed in semiconductor device physics books.
ContributorsYang, Xuan (Author) / Schroder, Dieter K. (Thesis advisor) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2011
Description
Semiconductor nanowires are featured by their unique one-dimensional structure which makes them promising for small scale electronic and photonic device applications. Among them, III-V material nanowires are particularly outstanding due to their good electronic properties. In bulk, these materials reveal electron mobility much higher than conventional silicon based devices, for example at room temperature, InAs field effect transistor (FET) has electron mobility of 40,000 cm2/Vs more than 10 times of Si FET. This makes such materials promising for high speed nanowire FETs. With small bandgap, such as 0.354 eV for InAs and 1.52 eV for GaAs, it does not need high voltage to turn on such devices which leads to low power consumption devices. Another feature of direct bandgap allows their applications of optoelectronic devices such as avalanche photodiodes. However, there are challenges to face up. Due to their large surface to volume ratio, nanowire devices typically are strongly affected by the surface states. Although nanowires can be grown into single crystal structure, people observe crystal defects along the wires which can significantly affect the performance of devices. In this work, FETs made of two types of III-V nanowire, GaAs and InAs, are demonstrated. These nanowires are grown by catalyst-free MOCVD growth method. Vertically nanowires are transferred onto patterned substrates for coordinate calibration. Then electrodes are defined by e-beam lithography followed by deposition of contact metals. Prior to metal deposition, however, the substrates are dipped in ammonium hydroxide solution to remove native oxide layer formed on nanowire surface. Current vs. source-drain voltage with different gate bias are measured at room temperature. GaAs nanowire FETs show photo response while InAs nanowire FETs do not show that. Surface passivation is performed on GaAs FETs by using ammonium surfide solution. The best results on current increase is observed with around 20-30 minutes chemical treatment time. Gate response measurements are performed at room temperature, from which field effect mobility as high as 1490 cm2/Vs is extracted for InAs FETs. One major contributor for this is stacking faults defect existing along nanowires. For InAs FETs, thermal excitations observed from temperature dependent results which leads us to investigate potential barriers.
ContributorsLiang, Hanshuang (Author) / Yu, Hongbin (Thesis advisor) / Ferry, David (Committee member) / Tracy, Clarence (Committee member) / Arizona State University (Publisher)
Created2011
Description
In this work, transport in nanowire materials and nanowire field effect transistors is studied using a full band Monte Carlo simulator within the tight binding basis. Chapter 1 is dedicated to the importance of nanowires and nanoscale devices in present day electronics and the necessity to use a computationally efficient tool to simulate transport in these devices. Chapter 2 discusses the calculation of the full band structure of nanowires based on an atomistic tight binding approach, particularly noting the use of the exact same tight binding parameters for bulk band structures as well as the nanowire band structures. Chapter 3 contains the scattering rate formula for deformation potential, polar optical phonon, ionized impurity and impact ionization scattering in nanowires using Fermi’s golden rule and the tight binding basis to describe the wave functions. A method to calculate the dielectric screening in 1D systems within the tight binding basis is also described. Importantly, the scattering rates of nanowires tends to the bulk scattering rates at high energies, enabling the use of the same parameter set that were fitted to bulk experimental data to be used in the simulation of nanowire transport. A robust and efficient method to model interband tunneling is discussed in chapter 4 and its importance in nanowire transport is highlighted. In chapter 5, energy relaxation of excited electrons is studied for free standing nanowires and cladded nanowires. Finally, in chapter 6, a full band Monte Carlo particle based solver is created which treats confinement in a full quantum way and the current voltage characteristics as well as the subthreshold swing and percentage of ballistic transport is analyzed for an In0.7Ga0.3As junctionless nanowire field effect transistor.
ContributorsHathwar, Raghuraj (Author) / Goodnick, Stephen M (Committee member) / Saraniti, Marco (Committee member) / Vasileska, Dragica (Committee member) / Ferry, David K. (Committee member) / Arizona State University (Publisher)
Created2016