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Description
This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic

This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic computing. First, experimental data from small signal, quasi-static and pulsed mode electrical characterization of such devices are presented which clearly demonstrate the inherent multi-level resistance programmability property in CBRAM devices. A physics based analytical CBRAM compact model is then presented which simulates the ion-transport dynamics and filamentary growth mechanism that causes resistance change in such devices. Simulation results from the model are fitted to experimental dynamic resistance switching characteristics. The model designed using Verilog-a language is computation-efficient and can be integrated with industry standard circuit simulation tools for design and analysis of hybrid circuits involving both CMOS and CBRAM devices. Three main circuit applications for CBRAM devices are explored in this work. Firstly, the susceptibility of CBRAM memory arrays to single event induced upsets is analyzed via compact model simulation and experimental heavy ion testing data that show possibility of both high resistance to low resistance and low resistance to high resistance transitions due to ion strikes. Next, a non-volatile sense amplifier based flip-flop architecture is proposed which can help make leakage power consumption negligible by allowing complete shutdown of power supply while retaining its output data in CBRAM devices. Reliability and energy consumption of the flip-flop circuit for different CBRAM low resistance levels and supply voltage values are analyzed and compared to CMOS designs. Possible extension of this architecture for threshold logic function computation using the CBRAM devices as re-configurable resistive weights is also discussed. Lastly, Spike timing dependent plasticity (STDP) based gradual resistance change behavior in CBRAM device fabricated in back-end-of-line on a CMOS die containing integrate and fire CMOS neuron circuits is demonstrated for the first time which indicates the feasibility of using CBRAM devices as electronic synapses in spiking neural network hardware implementations for non-Boolean neuromorphic computing.
ContributorsMahalanabis, Debayan (Author) / Barnaby, Hugh J. (Thesis advisor) / Kozicki, Michael N. (Committee member) / Vrudhula, Sarma (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Created2015
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Description
Total dose sensing systems (or radiation detection systems) have many applications,

ranging from survey monitors used to supervise the generated radioactive waste at

nuclear power plants to personal dosimeters which measure the radiation dose

accumulated in individuals. This dissertation work will present two different types of

novel devices developed at Arizona State University for

Total dose sensing systems (or radiation detection systems) have many applications,

ranging from survey monitors used to supervise the generated radioactive waste at

nuclear power plants to personal dosimeters which measure the radiation dose

accumulated in individuals. This dissertation work will present two different types of

novel devices developed at Arizona State University for total dose sensing applications.

The first detector technology is a mechanically flexible metal-chalcogenide glass (ChG)

based system which is fabricated on low cost substrates and are intended as disposable

total dose sensors. Compared to existing commercial technologies, these thin film

radiation sensors are simpler in form and function, and cheaper to produce and operate.

The sensors measure dose through resistance change and are suitable for applications

such as reactor dosimetry, radiation chemistry, and clinical dosimetry. They are ideal for

wearable devices due to the lightweight construction, inherent robustness to resist

breaking when mechanically stressed, and ability to attach to non-flat objects. Moreover,

their performance can be easily controlled by tuning design variables and changing

incorporated materials. The second detector technology is a wireless dosimeter intended

for remote total dose sensing. They are based on a capacitively loaded folded patch

antenna resonating in the range of 3 GHz to 8 GHz for which the load capacitance varies

as a function of total dose. The dosimeter does not need power to operate thus enabling

its use and implementation in the field without requiring a battery for its read-out. As a

result, the dosimeter is suitable for applications such as unattended detection systems

destined for covert monitoring of merchandise crossing borders, where nuclear material

tracking is a concern. The sensitive element can be any device exhibiting a known

variation of capacitance with total ionizing dose. The sensitivity of the dosimeter is

related to the capacitance variation of the radiation sensitive device as well as the high

frequency system used for reading. Both technologies come with the advantage that they

are easy to manufacture with reasonably low cost and sensing can be readily read-out.
ContributorsMahmud, Adnan, Ph.D (Author) / Barnaby, Hugh J. (Thesis advisor) / Kozicki, Michael N (Committee member) / Gonzalez-Velo, Yago (Committee member) / Goryll, Michael (Committee member) / Alford, Terry (Committee member) / Arizona State University (Publisher)
Created2017
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Description
Programmable Metallization Cell (PMC) technology has been shown to possess the necessary qualities for it to be considered as a leading contender for the next generation memory. These qualities include high speed and endurance, extreme scalability, ease of fabrication, ultra low power operation, and perhaps most importantly ease of integration

Programmable Metallization Cell (PMC) technology has been shown to possess the necessary qualities for it to be considered as a leading contender for the next generation memory. These qualities include high speed and endurance, extreme scalability, ease of fabrication, ultra low power operation, and perhaps most importantly ease of integration with the CMOS back end of line (BEOL) process flow. One area where detailed study is lacking is the reliability of PMC devices. In previous reliability work, the low and high resistance states were monitored for periods of hours to days without any applied voltage and the results were extrapolated to several years (>10) but little has been done to analyze the low resistance state under stress. With or without stress, the low resistance state appears to be highly stable but a gradual increase in resistance with time, less than one order of magnitude after ten years when extrapolated, has been observed. It is important to understand the physics behind this resistance rise mechanism to comprehend the reliability issues associated with the low resistance state. This is also related to the erase process in PMC cells where the transition from the ON to OFF state occurs under a negative voltage. Hence it is important to investigate this erase process in PMC cells under different conditions and to model it. Analyzing the programming and the erase operations separately is important for any memory technology but its ability to cycle efficiently (reliably) at low voltages and for more than 1E4 cycles (without affecting the cells performance) is more critical. Future memory technologies must operate with the low power supply voltages (<1V) required for small geometry nodes. Low voltage programming of PMC memory devices has previously been demonstrated using slow voltage sweeps and small numbers of fast pulses. In this work PMC memory cells were cycled at low voltages using symmetric pulses with different load resistances and the distribution of the ON and OFF resistances was analyzed. The effect of the program current used during the program-erase cycling on the resulting resistance distributions is also investigated. Finally the variation found in the behavior of similar resistance ON states in PMC cells was analyzed more in detail and measures to reduce this variation were looked into. It was found that slow low current programming helped reducing the variation in erase times of similar resistance ON states in PMC cells. This scheme was also used as a pre-conditioning technique and the improvements in subsequent cycling behavior were compared.
ContributorsKamalanathan, Deepak (Author) / Kozicki, Dr. Michael (Thesis advisor) / Schroder, Dr. Dieter (Committee member) / Goryll, Dr. Michael (Committee member) / Alford, Dr. Terry (Committee member) / Arizona State University (Publisher)
Created2011