Matching Items (15)
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- All Subjects: Integrated circuits
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- Genre: Masters Thesis
- Creators: Bakkaloglu, Bertan
- Creators: Kiaei, Sayfe
- Member of: ASU Electronic Theses and Dissertations
Description
Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and oxide thickness fluctuation. These variations greatly impact all aspects of circuit performance and pose a grand challenge to future robust IC design. To improve robustness, efficient methodology is required that considers effect of variations in the design flow. Analyzing timing variability of complex circuits with HSPICE simulations is very time consuming. This thesis proposes an analytical model to predict variability in CMOS circuits that is quick and accurate. There are several analytical models to estimate nominal delay performance but very little work has been done to accurately model delay variability. The proposed model is comprehensive and estimates nominal delay and variability as a function of transistor width, load capacitance and transition time. First, models are developed for library gates and the accuracy of the models is verified with HSPICE simulations for 45nm and 32nm technology nodes. The difference between predicted and simulated σ/μ for the library gates is less than 1%. Next, the accuracy of the model for nominal delay is verified for larger circuits including ISCAS'85 benchmark circuits. The model predicted results are within 4% error of HSPICE simulated results and take a small fraction of the time, for 45nm technology. Delay variability is analyzed for various paths and it is observed that non-critical paths can become critical because of Vth variation. Variability on shortest paths show that rate of hold violations increase enormously with increasing Vth variation.
ContributorsGummalla, Samatha (Author) / Chakrabarti, Chaitali (Thesis advisor) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
Optical receivers have many different uses covering simple infrared receivers, high speed fiber optic communication and light based instrumentation. All of them have an optical receiver that converts photons to current followed by a transimpedance amplifier to convert the current to a useful voltage. Different systems create different requirements for each receiver. High speed digital communication require high throughput with enough sensitivity to keep the bit error rate low. Instrumentation receivers have a lower bandwidth, but higher gain and sensitivity requirements. In this thesis an optical receiver for use in instrumentation in presented. It is an entirely monolithic design with the photodiodes on the same substrate as the CMOS circuitry. This allows for it to be built into a focal-plane array, but it places some restriction on the area. It is also designed for in-situ testing and must be able to cancel any low frequency noise caused by ambient light. The area restrictions prohibit the use of a DC blocking capacitor to reject the low frequency noise. In place a servo loop was wrapped around the system to reject any DC offset. A modified Cherry-Hooper architecture was used for the transimpedance amplifier. This provides the flexibility to create an amplifier with high gain and wide bandwidth that is independent of the input capacitance. The downside is the increased complexity of the design makes stability paramount to the design. Another drawback is the high noise associated with low input impedance that decouples the input capacitance from the bandwidth. This problem is compounded by the servo loop feed which leaves the output noise of some amplifiers directly referred to the input. An in depth analysis of each circuit block's noise contribution is presented.
ContributorsLaFevre, Kyle (Author) / Bakkaloglu, Bertan (Thesis advisor) / Barnaby, Hugh (Committee member) / Vermeire, Bert (Committee member) / Arizona State University (Publisher)
Created2011
Description
Digital to analog converters (DACs) find widespread use in communications equipment. Most commercially available DAC's which are intended to be used in transmitter applications come in a dual configuration for carrying the in phase (I) and quadrature (Q) data and feature on chip digital mixing. Digital mixing offers many benefits concerning I and Q matching but has one major drawback; the update rate of the DAC must be higher than the intermediate frequency (IF) which is most commonly a factor of 4. This drawback motivates the need for interpolation so that a low update rate can be used for components preceding the DACs. In this thesis the design of an interpolating DAC integrated circuit (IC) to be used in a transmitter application for generating a 100MHz IF is presented. Many of the transistor level implementations are provided. The tradeoffs in the design are analyzed and various options are discussed. This thesis provides a basic foundation for designing an IC of this nature and will give the reader insight into potential areas of further research. At the time of this writing the chip is in fabrication therefore this document does not contain test results.
ContributorsNixon, Cliff (Author) / Bakkaloglu, Bertan (Thesis advisor) / Arizona State University (Publisher)
Created2013
Description
Mobile electronic devices such as smart phones, netbooks and tablets have seen increasing demand in recent years, and so has the need for efficient, responsive and small power management solutions that are integrated into these devices. Every thing from the battery life to the screen brightness to how warm the device gets depends on the power management solution integrated within the device. Much of the future success of these mobile devices will depend on innovative, reliable and efficient power solutions. Perhaps this is one of the drivers behind the intense research activity seen in the power management field in recent years. The demand for higher accuracy regulation and fast response in switching converters has led to the exploration of digital control techniques as a way to implement more advanced control architectures. In this thesis, a novel digitally controlled step-down (buck) switching converter architecture that makes use of switched capacitors to improve the transient response is presented. Using the proposed architecture, the transient response is improved by a factor of two or more in comparison to the theoretical limits that can be achieved with a basic step down converter control architecture. The architecture presented in this thesis is not limited to digitally controlled topologies but rather can also be used in analog topologies as well. Design and simulation results of a 1.8V, 15W, 1MHz digitally controlled step down converter with a 12mV Analog to Digital Converter (ADC) resolution and a 2ns DPWM (Digital Pulse Width Modulator) resolution are presented.
ContributorsHashim, Ahmed (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2013
Description
The front end of almost all ADCs consists of a Sample and Hold Circuit in order to make sure a constant analog value is digitized at the end of ADC. The design of Track and Hold Circuit (THA) mainly focuses on following parameters: Input frequency, Sampling frequency, dynamic Range, hold pedestal, feed through error. This thesis will discuss the importance of these parameters of a THA to the ADCs and commonly used architectures of THA. A new architecture with SiGe HBT transistors in BiCMOS 130 nm technology is presented here. The proposed topology without complicated circuitry achieves high Spurious Free Dynamic Range(SFDR) and Total Harmonic Distortion (THD).These are important figure of merits for any THA which gives a measure of non-linearity of the circuit. The proposed topology is implemented in IBM8HP 130 nm BiCMOS process combines typical emitter follower switch in bipolar THAs and output steering technique proposed in the previous work. With these techniques and the cascode transistor in the input which is used to isolate the switch from the input during the hold mode, better results have been achieved. The THA is designed to work with maximum input frequency of 250 MHz at sampling frequency of 500 MHz with input currents not more than 5mA achieving an SFDR of 78.49 dB. Simulation and results are presented, illustrating the advantages and trade-offs of the proposed topology.
ContributorsRao, Nishita Ramakrishna (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
Description
With the rapid expansion of the photovoltaic industry over the last decade, there has been a huge demand in the PV installations in the residential sector. This thesis focuses on the analysis and implementation of a dc-dc boost converter at photovoltaic sub-module level. The thesis also analyses the various topologies like switched capacitors and extended duty ratio which can be practically implemented in the photovoltaic panels. The results obtained in this work have concentrated on the use of novel strategies to substitute the use of central dc-dc converter used in PV module string connection. The implementation of distributed MPPT at the PV sub-module level is also an integral part of this thesis. Using extensive PLECS simulations, this thesis came to the conclusion that with the design of a proper compensation at the dc interconnection of a series or parallel PV Module Integrated Converter string, the central dc-dc converter can be substituted. The dc-ac interconnection voltage remains regulated at all irradiance level even without a dc-dc central converter at the string end. The foundation work for the hardware implementation has also been carried out. Design of parameters for future hardware implementation has also been presented in detail in this thesis.
ContributorsSen, Sourav (Author) / Ayyanar, Raja (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2012
Description
Power Management circuits are employed in almost all electronic equipment and they have energy storage elements (capacitors and inductors) as building blocks along with other active circuitry. Power management circuits employ feedback to achieve good load and line regulation. The feedback loop is designed at an operating point and component values are chosen to meet that design requirements. But the capacitors and inductors are subject to variations due to temperature, aging and load stress. Due to these variations, the feedback loop can cross its robustness margins and can lead to degraded performance and potential instability. Another issue in power management circuits is the measurement of their frequency response for stability assessment. The standard techniques used in production test environment require expensive measurement equipment (Network Analyzer) and time. These two issues of component variations and frequency response measurement can be addressed if the frequency response of the power converter is used as measure of component (capacitor and inductor) variations. So, a single solution of frequency response measurement solves both the issues. This work examines system identification (frequency response measurement) of power management circuits based on cross correlation technique and proposes the use of switched capacitor correlator for this purpose. A switched capacitor correlator has been designed and used in the system identification of Linear and Switching regulators. The obtained results are compared with the standard frequency response measurement methods of power converters.
ContributorsMalladi, Venkata Naga Koushik (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2015
Description
The photovoltaic systems used to convert solar energy to electricity pose a multitude of design and implementation challenges, including energy conversion efficiency, partial shading effects, and power converter efficiency. Using power converters for Distributed Maximum Power Point Tracking (DMPPT) is a well-known architecture to significantly reduce power loss associated with mismatched panels. Sub-panel-level DMPPT is shown to have up to 14.5% more annual energy yield than panel-level DMPPT, and requires an efficient medium power converter.
This research aims at implementing a highly efficient power management system at sub-panel level with focus on system cost and form-factor. Smaller form-factor motivates increased converter switching frequencies to significantly reduce the size of converter passives and substantially improve transient performance. But, currently available power MOSFETs put a constraint on the highest possible switching frequency due to increased switching losses. The solution is Gallium Nitride based power devices, which deliver figure of merit (FOM) performance at least an order of magnitude higher than existing silicon MOSFETs. Low power loss, high power density, low cost and small die sizes are few of the qualities that make e-GaN superior to its Si counterpart. With careful design, e-GaN can enable a 20-30% improvement in power stage efficiency compared to converters using Si MOSFETs.
The main objective of this research is to develop a highly integrated, high efficiency, 20MHz, hybrid GaN-CMOS DC-DC MPPT converter for a 12V/5A sub-panel. Hard and soft switching boost converter topologies are investigated within this research, and an innovative CMOS gate drive technique for efficiently driving an e-GaN power stage is presented in this work. The converter controller also employs a fast converging analog MPPT control technique.
This research aims at implementing a highly efficient power management system at sub-panel level with focus on system cost and form-factor. Smaller form-factor motivates increased converter switching frequencies to significantly reduce the size of converter passives and substantially improve transient performance. But, currently available power MOSFETs put a constraint on the highest possible switching frequency due to increased switching losses. The solution is Gallium Nitride based power devices, which deliver figure of merit (FOM) performance at least an order of magnitude higher than existing silicon MOSFETs. Low power loss, high power density, low cost and small die sizes are few of the qualities that make e-GaN superior to its Si counterpart. With careful design, e-GaN can enable a 20-30% improvement in power stage efficiency compared to converters using Si MOSFETs.
The main objective of this research is to develop a highly integrated, high efficiency, 20MHz, hybrid GaN-CMOS DC-DC MPPT converter for a 12V/5A sub-panel. Hard and soft switching boost converter topologies are investigated within this research, and an innovative CMOS gate drive technique for efficiently driving an e-GaN power stage is presented in this work. The converter controller also employs a fast converging analog MPPT control technique.
ContributorsKrishnan Achary, Kiran Kumar (Author) / Kitchen, Jennifer (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2015
Description
The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to provide clean supply for low voltage integrated circuits, where point-of-load regulation is important. In System-On-Chip (SoC) applications, digital circuits can change their mode of operation regularly at a very high speed, imposing various load transient conditions for the regulator. These quick changes of load create a glitch in LDO output voltage, which hamper performance of the digital circuits unfavorably. For an LDO designer, minimizing output voltage variation and speeding up voltage glitch settling is an important task.
The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
ContributorsDesai, Chirag (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2016
Description
A single solar cell provides close to 0.5 V output at its maximum power point, which is very
low for any electronic circuit to operate. To get rid of this problem, traditionally multiple
solar cells are connected in series to get higher voltage. The disadvantage of this approach
is the efficiency loss for partial shading or mismatch. Even as low as 6-7% of shading can
result in more than 90% power loss. Therefore, Maximum Power Point Tracking (MPPT)
at single solar cell level is the most efficient way to extract power from solar cell.
Power Management IC (MPIC) used to extract power from single solar cell, needs to
start at 0.3 V input. MPPT circuitry should be implemented with minimal power and area
overhead. To start the PMIC at 0.3 V, a switch capacitor charge pump is utilized as an
auxiliary start up circuit for generating a regulated 1.8 V auxiliary supply from 0.3 V input.
The auxiliary supply powers up a MPPT converter followed by a regulated converter. At
the start up both the converters operate at 100 kHz clock with 80% duty cycle and system
output voltage starts rising. When the system output crosses 2.7 V, the auxiliary start up
circuit is turned off and the supply voltage for both the converters is derived from the system
output itself. In steady-state condition the system output is regulated to 3.0 V.
A fully integrated analog MPPT technique is proposed to extract maximum power from
the solar cell. This technique does not require Analog to Digital Converter (ADC) and
Digital Signal Processor (DSP), thus reduces area and power overhead. The proposed
MPPT techniques includes a switch capacitor based power sensor which senses current of
boost converter without using any sense resistor. A complete system is designed which
starts from 0.3 V solar cell voltage and provides regulated 3.0 V system output.
low for any electronic circuit to operate. To get rid of this problem, traditionally multiple
solar cells are connected in series to get higher voltage. The disadvantage of this approach
is the efficiency loss for partial shading or mismatch. Even as low as 6-7% of shading can
result in more than 90% power loss. Therefore, Maximum Power Point Tracking (MPPT)
at single solar cell level is the most efficient way to extract power from solar cell.
Power Management IC (MPIC) used to extract power from single solar cell, needs to
start at 0.3 V input. MPPT circuitry should be implemented with minimal power and area
overhead. To start the PMIC at 0.3 V, a switch capacitor charge pump is utilized as an
auxiliary start up circuit for generating a regulated 1.8 V auxiliary supply from 0.3 V input.
The auxiliary supply powers up a MPPT converter followed by a regulated converter. At
the start up both the converters operate at 100 kHz clock with 80% duty cycle and system
output voltage starts rising. When the system output crosses 2.7 V, the auxiliary start up
circuit is turned off and the supply voltage for both the converters is derived from the system
output itself. In steady-state condition the system output is regulated to 3.0 V.
A fully integrated analog MPPT technique is proposed to extract maximum power from
the solar cell. This technique does not require Analog to Digital Converter (ADC) and
Digital Signal Processor (DSP), thus reduces area and power overhead. The proposed
MPPT techniques includes a switch capacitor based power sensor which senses current of
boost converter without using any sense resistor. A complete system is designed which
starts from 0.3 V solar cell voltage and provides regulated 3.0 V system output.
ContributorsSingh, Shrikant (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2015