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- All Subjects: Metal oxide semiconductors, Complementary
- All Subjects: RF
- Creators: Kitchen, Jennifer
- Creators: Blain Christen, Jennifer
Description
This thesis describes the design process used in the creation of a two stage cellular power amplifier. A background for understanding amplifier linearity, device properties, and ACLR estimation is provided. An outline of the design goals is given with a focus on linearity with high efficiency. The full design is broken into smaller elements which are discussed in detail. The main contribution of this thesis is the description of a novel interstage matching network topology for increasing efficiency. Ultimately the full amplifier design is simulated and compared to the measured results and design goals. It was concluded that the design was successful, and used in a commercially available product.
ContributorsSpivey, Erin (Author) / Aberle, James T., 1961- (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2012
Description
The world has seen a revolution in cellular communication with the advent of 5G, which enables gigabits per second data speed with low latency, massive capacity, and increased availability. Complex modulated signals are used in these moderncommunication systems to achieve high spectral efficiency, and these signals exhibit high peak to average power ratios (PAPR). Design of cellular infrastructure hardware to support these complex signals therefore becomes challenging, as the transmitter’s radio frequency power amplifier (RF PA) needs to remain highly efficient at both peak and backed off power conditions. Additionally, these PAs should exhibit high linearity and support continually increasing bandwidths. Many advanced PA configurations exhibit high efficiency for processing legacy communications signals. Some of the most popular architectures are Envelope Elimination and Restoration (EER), Envelope Tracking (ET), Linear Amplification using Non-linear Component (LINC), Doherty Power Amplifiers (DPA), and Polar Transmitters. Among these techniques,
the DPA is the most widely used architecture for base-station applications because of its simple configuration and ability to be linearized using simple digital pre-distortion (DPD) algorithms. To support the cellular infrastructure needs of 5G and beyond, RF PAs, specifically DPA architectures, must be further enhanced to support broader bandwidths as well as smaller form-factors with higher levels of integration. The following four novel works are presented in this dissertation to support RF PA requirements for future cellular infrastructure:
1. A mathematical analysis to analyze the effects of non-linear parasitic capacitance (Cds) on the operation of continuous class-F (CCF) mode power amplifiers and identify their optimum operating range for high power and efficiency.
2. A methodology to incorporate a class-J harmonic trapping network inside the PA package by considering the effect of non-linear Cds, thus reducing the DPA footprint while achieving high RF performance.
3. A novel method of synthesizing the DPA’s output combining network (OCN) to realize an integrated two-stage integrated LDMOS asymmetric DPA.
4. A novel extended back-off efficiency range DPA architecture that engineers the mutual interaction between combining load and peaking off-state impedance. The theory and architecture are verified through a GaN-based DPA design.
ContributorsAhmed, Maruf Newaz (Author) / Kitchen, Jennifer (Thesis advisor) / Aberle, James (Committee member) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2022
Description
This research explores the potential use of microwave energy to detect various substances in water, with a focus on water quality assessment and pathogen detection applications. There are many non-thermal effects of microwaves on microorganisms and their resonant frequencies could be used to identify and possibly destroy harmful pathogens, such as bacteria and viruses, without heating the water. A wide range of materials, including living organisms like Daphnia and Moina, plants, sand, plastic, and salt, were subjected to microwave measurements to assess their influence on the transmission (S21) measurements. The measurements of the living organisms did not display distinctive resonant frequencies and variations in water volume may be the source of the small measurement differences. Conversely, sand and plastic pellets affected the measurements differently, with their arrangement within the test tube emerging as a significant factor. This study also explores the impact of salinity on measurements, revealing a clear pattern that can be modeled as a series RLC resonator. Although unique resonant frequencies for the tested organisms were not identified, the presented system demonstrates the potential for detecting contaminants based on variations in measurements. Future research may extend this work to include a broader array of organisms and enhance measurement precision.
ContributorsChild, Carson (Author) / Aberle, James (Thesis director) / Blain Christen, Jennifer (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2023-12
Description
The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power ratio (PAPR) even after applying crest factor reduction. Being the most power-hungry component in the radio frequency (RF) transmitter, power amplifiers (PA) for infrastructure applications, need to operate efficiently at the presence of these high PAPR signals while maintaining reasonable linearity performance which could be improved by moderate digital pre-distortion (DPD) techniques. This strict requirement of operating efficiently at average power level while being capable of delivering the peak power, made the load modulated PAs such as Doherty PA, Outphasing PA, various Envelope Tracking PAs, Polar transmitters and most recently the load modulated balanced PA, the prime candidates for such application. However, due to its simpler architecture and ability to deliver RF power efficiently with good linearity performance has made Doherty PA (DPA) the most popular solution and has been deployed almost exclusively for wireless infrastructure application all over the world.
Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels.
Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels.
ContributorsRuhul Hasin, Muhammad (Author) / Kitchen, Jennifer (Thesis advisor) / Aberle, James T., 1961- (Committee member) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2018
Description
Rail clamp circuits are widely used for electrostatic discharge (ESD) protection in semiconductor products today. A step-by-step design procedure for the traditional RC and single-inverter-based rail clamp circuit and the design, simulation, implementation, and operation of two novel rail clamp circuits are described for use in the ESD protection of complementary metal-oxide-semiconductor (CMOS) circuits. The step-by-step design procedure for the traditional circuit is technology-node independent, can be fully automated, and aims to achieve a minimal area design that meets specified leakage and ESD specifications under all valid process, voltage, and temperature (PVT) conditions. The first novel rail clamp circuit presented employs a comparator inside the traditional circuit to reduce the value of the time constant needed. The second circuit uses a dynamic time constant approach in which the value of the time constant is dynamically adjusted after the clamp is triggered. Important metrics for the two new circuits such as ESD performance, latch-on immunity, clamp recovery time, supply noise immunity, fastest power-on time supported, and area are evaluated over an industry-standard PVT space using SPICE simulations and measurements on a fabricated 40 nm test chip.
ContributorsVenkatasubramanian, Ramachandran (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2016
Description
This thesis dissertation presents design of portable low power Electrochemical Impedance Spectroscopy (EIS) system which can be used for biomedical applications such as tear diagnosis, blood diagnosis, or any other body-fluid diagnosis. Two design methodologies are explained in this dissertation (a) a discrete component-based portable low-power EIS system and (b) an integrated CMOS-based portable low-power EIS system. Both EIS systems were tested in a laboratory environment and the characterization results are compared. The advantages and disadvantages of the integrated EIS system relative to the discrete component-based EIS system are presented including experimental data. The specifications of both EIS systems are compared with commercially available non-portable EIS workstations. These designed EIS systems are handheld and very low-cost relative to the currently available commercial EIS workstations.
ContributorsGhorband, Vishal (Author) / Blain Christen, Jennifer (Thesis advisor) / Song, Hongjiang (Committee member) / LaBelle, Jeffrey (Committee member) / Arizona State University (Publisher)
Created2016
Description
In-band full-duplex relays are envisioned as promising solution to increase the throughput of next generation wireless communications. Full-duplex relays, being able to transmit and receive at same carrier frequency, offers increased spectral efficiency compared to half-duplex relays that transmit and receive at different frequencies or times. The practical implementation of full-duplex relays is limited by the strong self-interference caused by the coupling of relay's own transit signals to its desired received signals. Several techniques have been proposed in literature to mitigate the relay self-interference. In this thesis, the performance of in-band full-duplex multiple-input multiple-output (MIMO) relays is considered in the context of simultaneous communications and channel estimation. In particular, adaptive spatial transmit techniques is considered to protect the full-duplex radio's receive array. It is assumed that relay's transmit and receive antenna phase centers are physically distinct. This allows the radio to employ adaptive spatial transmit and receive processing to mitigate self-interference.
The performance of this protection is dependent upon numerous factors, including channel estimation accuracy, which is the focus of this thesis. In particular, the concentration is on estimating the self-interference channel. A novel approach of simultaneous signaling to estimate the self-interference channel in MIMO full-duplex relays is proposed. To achieve this simultaneous communications
and channel estimation, a full-rank pilot signal at a reduced relative power is transmitted simultaneously with a low rank communication waveform. The self-interference mitigation is investigated in the context of eigenvalue spread of spatial relay receive co-variance matrix. Performance is demonstrated by using simulations,
in which orthogonal-frequency division-multiplexing communications and pilot sequences are employed.
The performance of this protection is dependent upon numerous factors, including channel estimation accuracy, which is the focus of this thesis. In particular, the concentration is on estimating the self-interference channel. A novel approach of simultaneous signaling to estimate the self-interference channel in MIMO full-duplex relays is proposed. To achieve this simultaneous communications
and channel estimation, a full-rank pilot signal at a reduced relative power is transmitted simultaneously with a low rank communication waveform. The self-interference mitigation is investigated in the context of eigenvalue spread of spatial relay receive co-variance matrix. Performance is demonstrated by using simulations,
in which orthogonal-frequency division-multiplexing communications and pilot sequences are employed.
ContributorsSekhar, Kishore Kumar (Author) / Bliss, Daniel W (Thesis advisor) / Kitchen, Jennifer (Committee member) / Zhang, Junshan (Committee member) / Arizona State University (Publisher)
Created2014
Description
Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
ContributorsPadala, Sudheer (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below:
1) A transformer-based power combiner architecture for out-phasing transmitters
2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)
3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters
This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.
The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.
Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.
1) A transformer-based power combiner architecture for out-phasing transmitters
2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)
3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters
This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.
The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.
Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.
ContributorsMoallemi, Soroush (Author) / Kitchen, Jennifer (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2019