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NGExtract 2: MOSFET Parameter Extraction Tool

Description
NGExtract 2 is a complete transistor (MOSFET) parameter extraction solution based upon the original computer program NGExtract by Rahul Shringarpure written in February 2007. NGExtract 2 is written in Java and based around the circuit simulator NGSpice. The goal of the program is to be used to produce…

NGExtract 2 is a complete transistor (MOSFET) parameter extraction solution based upon the original computer program NGExtract by Rahul Shringarpure written in February 2007. NGExtract 2 is written in Java and based around the circuit simulator NGSpice. The goal of the program is to be used to produce accurate transistor models based around real-world transistor data. The program contains numerous improvements to the original program:
• Completely rewritten with performance and usability in mind
• Cross-Platform vs. Linux Only
• Simple installation procedure vs. compilation and manual library configuration
• Self-contained, single file runtime
• Particle Swarm Optimization routine
NGExtract 2 works by plotting the Ids vs. Vds and Ids vs. Vgs curves of a simulation model and the measured, real-world data. The user can adjust model parameters and re-simulate to attempt to match the curves. The included Particle Swarm Optimization routine attempts to automate this process by iteratively attempting to improve a solution by measuring its sum-squared error against the real-world data that the user has provided.
ContributorsVetrano, Michael Thomas (Author) / Allee, David (Thesis director) / Gorur, Ravi (Committee member) / Bakkaloglu, Bertan (Committee member) / Barrett, The Honors College (Contributor) / Computer Science and Engineering Program (Contributor)
Created2013-05
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Redundant skewed clocking of pulse-clocked latches for low power soft-error mitigation

Description
An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced power consumption. This methodology helps to change the hardness of the design on the fly. This approach, with minimal additional overhead circuitry, has the ability…

An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced power consumption. This methodology helps to change the hardness of the design on the fly. This approach, with minimal additional overhead circuitry, has the ability to work in three different modes of operation depending on the speed, hardness and power consumption required by design. This was designed on 90nm low-standby power (LSP) process and utilized commercial CAD tools for testing. Spatial separation of critical nodes in the physical design of this approach mitigates multi-node charge collection (MNCC) upsets. An advanced encryption system implemented with the proposed design, compared to a previous design with non-redundant clock trees and local delay generation. The proposed approach reduces energy per operation up to 18% over an improved version of the prior approach, with negligible area impact. It can save up to 2/3rd of the power consumption and reach maximum possible frequency, when used in non-redundant mode of operation.
ContributorsGujja, Aditya (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2015