Matching Items (4)
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- All Subjects: CMOS
- Creators: Aberle, James T., 1961-
- Creators: Burton, Richard
Description
Semiconductor device scaling has kept up with Moore's law for the past decades and they have been scaling by a factor of half every one and half years. Every new generation of device technology opens up new opportunities and challenges and especially so for analog design. High speed and low gain is characteristic of these processes and hence a tradeoff that can enable to get back gain by trading speed is crucial. This thesis proposes a solution that increases the speed of sampling of a circuit by a factor of three while reducing the specifications on analog blocks and keeping the power nearly constant. The techniques are based on the switched capacitor technique called Correlated Level Shifting. A triple channel Cyclic ADC has been implemented, with each channel working at a sampling frequency of 3.33MS/s and a resolution of 14 bits. The specifications are compared with that based on a traditional architecture to show the superiority of the proposed technique.
ContributorsSivakumar, Balasubramanian (Author) / Farahani, Bahar Jalali (Thesis advisor) / Garrity, Douglas (Committee member) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2012
Description
ABSTRACT Ongoing research into wireless transceivers in the 60 GHz band is required to address the demand for high data rate communications systems at a frequency where signal propagation is challenging even over short ranges. This thesis proposes a mixer architecture in Complementary Metal Oxide Semiconductor (CMOS) technology that uses a voltage controlled oscillator (VCO) operating at a fractional multiple of the desired output signal. The proposed topology is different from conventional subharmonic mixing in that the oscillator phase generation circuitry usually required for such a circuit is unnecessary. Analysis and simulations are performed on the proposed mixer circuit in an IBM 90 nm RF process on a 1.2 V supply. A typical RF transmitter system is considered in determining the block requirements needed for the mixer to meet the IEEE 802.11ad 60 GHz Draft Physical Layer Specification. The proposed circuit has a conversion loss of 21 dB at 60 GHz with a 5 dBm LO power at 20 GHz. Input-referred third-order intercept point (IIP3) is 2.93 dBm. The gain and linearity of the proposed mixer are sufficient for Orthogonal Frequency Division Multiplexing (OFDM) modulation at 60 GHz with a transmitted data rate of over 4 Gbps.
ContributorsMartino, Todd Jeffrey (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2010
Description
This dissertation explores thermal effects and electrical characteristics in metal-oxide-semiconductor field effect transistor (MOSFET) devices and circuits using a multiscale dual-carrier approach. Simulating electron and hole transport with carrier-phonon interactions for thermal transport allows for the study of complementary logic circuits with device level accuracy in electrical characteristics and thermal effects. The electrical model is comprised of an ensemble Monte Carlo solution to the Boltzmann Transport Equation coupled with an iterative solution to two-dimensional (2D) Poisson’s equation. The thermal model solves the energy balance equations accounting for carrier-phonon and phonon-phonon interactions. Modeling of circuit behavior uses parametric iteration to ensure current and voltage continuity. This allows for modeling of device behavior, analyzing circuit performance, and understanding thermal effects.
The coupled electro-thermal approach, initially developed for individual n-channel MOSFET (NMOS) devices, now allows multiple devices in tandem providing a platform for better comparison with heater-sensor experiments. The latest electro-thermal solver allows simulation of multiple NMOS and p-channel MOSFET (PMOS) devices, providing a platform for the study of complementary MOSFET (CMOS) circuit behavior. Modeling PMOS devices necessitates the inclusion of hole transport and hole-phonon interactions. The analysis of CMOS circuits uses the electro-thermal device simulation methodology alongside parametric iteration to ensure current continuity. Simulating a CMOS inverter and analyzing the extracted voltage transfer characteristics verifies the efficacy of this methodology. This work demonstrates the effectiveness of the dual-carrier electro-thermal solver in simulating thermal effects in CMOS circuits.
The coupled electro-thermal approach, initially developed for individual n-channel MOSFET (NMOS) devices, now allows multiple devices in tandem providing a platform for better comparison with heater-sensor experiments. The latest electro-thermal solver allows simulation of multiple NMOS and p-channel MOSFET (PMOS) devices, providing a platform for the study of complementary MOSFET (CMOS) circuit behavior. Modeling PMOS devices necessitates the inclusion of hole transport and hole-phonon interactions. The analysis of CMOS circuits uses the electro-thermal device simulation methodology alongside parametric iteration to ensure current continuity. Simulating a CMOS inverter and analyzing the extracted voltage transfer characteristics verifies the efficacy of this methodology. This work demonstrates the effectiveness of the dual-carrier electro-thermal solver in simulating thermal effects in CMOS circuits.
ContributorsDaugherty, Robin (Author) / Vasileska, Dragica (Thesis advisor) / Aberle, James T., 1961- (Committee member) / Ferry, David (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2019
Description
This thesis presents three novel studies. The first two works focus on galvanically isolated chip-to-chip communication, and the third research studies class-E pulse-width modulated power amplifiers. First, a common-mode resilient CMOS (complementary metal-oxide-semiconductor) galvanically isolated Radio Frequency (RF) chip-to-chip communication system is presented utilizing laterally resonant coupled circuits to increases maximum common-mode transient immunity and the isolation capability of galvanic isolators in a low-cost standard CMOS solution beyond the limits provided from the vertical coupling. The design provides the highest reported CMTI (common-mode transient immunity) of more than 600 kV/µs, 5 kVpk isolation, and a chip area of 0.95 mm2. In the second work, a bi-directional ultra-wideband transformer-coupled galvanic isolator is reported for the first time. The proposed design merges the functionality of two isolated channels into one magnetically coupled communication, enabling up to 50% form-factor and assembly cost reduction while achieving a simultaneously robust and state-of-art performance. This work achieves simultaneous robust, wideband, and energy-efficient performance of 300 Mb/s data rate, isolation of 7.8 kVrms, and power consumption and propagation delay of 200 pJ/b and 5 ns, respectively, in only 0.8 mm2 area. The third works studies class-E pulse-width modulated (PWM) Power amplifiers (PAs). For the first time, it presents a design technique to significantly extend the Power back-off (PBO) dynamic range of PWM PAs over the prior art. A proof-of-concept watt-level class-E PA is designed using a GaN HEMT and exhibits more than 6dB dynamic range for a 50 to 30 percent duty cycle variation. Moreover, in this work, the effects of non-idealities on performance and design of class-E power amplifiers for variable supply on and pulse-width operations are characterized and studied, including the effect of non-linear parasitic capacitances and its exploitation for enhancement of average efficiency and self-heating effects in class-E SMPAs using a new over dry-ice measurement technique was presented for this first time. The non-ideality study allows for capturing a full view of the design requirement and considerations of class-E power amplifiers and provides a window to the phenomena that lead to a mismatch between the ideal and actual performance of class-E power amplifiers and their root causes.
ContributorsJavidahmadabadi, Mahdi (Author) / Kitchen, Jennifer N (Thesis advisor) / Aberle, James (Committee member) / Bakkaloglu, Bertan (Committee member) / Burton, Richard (Committee member) / Arizona State University (Publisher)
Created2021