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Description
Traditional approaches to modeling microgrids include the behavior of each inverter operating in a particular network configuration and at a particular operating point. Such models quickly become computationally intensive for large systems. Similarly, traditional approaches to control do not use advanced methodologies and suffer from poor performance and limited operating range. In this document a linear model is derived for an inverter connected to the Thevenin equivalent of a microgrid. This model is then compared to a nonlinear simulation model and analyzed using the open and closed loop systems in both the time and frequency domains. The modeling error is quantified with emphasis on its use for controller design purposes. Control design examples are given using a Glover McFarlane controller, gain sched- uled Glover McFarlane controller, and bumpless transfer controller which are compared to the standard droop control approach. These examples serve as a guide to illustrate the use of multi-variable modeling techniques in the context of robust controller design and show that gain scheduled MIMO control techniques can extend the operating range of a microgrid. A hardware implementation is used to compare constant gain droop controllers with Glover McFarlane controllers and shows a clear advantage of the Glover McFarlane approach.
ContributorsSteenis, Joel (Author) / Ayyanar, Raja (Thesis advisor) / Mittelmann, Hans (Committee member) / Tsakalis, Konstantinos (Committee member) / Tylavsky, Daniel (Committee member) / Arizona State University (Publisher)
Created2013
Description
Multiple-input multiple-output systems have gained focus in the last decade due to the benefits they provide in enhancing the quality of communications. On the other hand, full-duplex communication has attracted remarkable attention due to its ability to improve the spectral efficiency compared to the existing half-duplex systems. Using full-duplex communications on MIMO co-operative networks can provide us solutions that can completely outperform existing systems with simultaneous transmission and reception at high data rates.
This thesis considers a full-duplex MIMO relay which amplifies and forwards the received signals, between a source and a destination that do not a have line of sight. Full-duplex mode raises the problem of self-interference. Though all the links in the system undergo frequency flat fading, the end-to-end effective channel is frequency selective. This is due to the imperfect cancellation of the self-interference at the relay and this residual self-interference acts as intersymbol interference at the destination which is treated by equalization. This also leads to complications in form of recursive equations to determine the input-output relationship of the system. This also leads to complications in the form of recursive equations to determine the input-output relationship of the system.
To overcome this, a signal flow graph approach using Mason's gain formula is proposed, where the effective channel is analyzed with keen notice to every loop and path the signal traverses. This gives a clear understanding and awareness about the orders of the polynomials involved in the transfer function, from which desired conclusions can be drawn. But the complexity of Mason's gain formula increases with the number of antennas at relay which can be overcome by the proposed linear algebraic method. Input-output relationship derived using simple concepts of linear algebra can be generalized to any number of antennas and the computation complexity is comparatively very low.
For a full-duplex amplify-and-forward MIMO relay system, assuming equalization at the destination, new mechanisms have been implemented at the relay that can compensate the effect of residual self-interference namely equal-gain transmission and antenna selection. Though equal-gain transmission does not perform better than the maximal ratio transmission, a trade-off can be made between performance and implementation complexity. Using the proposed antenna selection strategy, one pair of transmit-receive antennas at the relay is selected based on four selection criteria discussed. Outage probability analysis is performed for all the strategies presented and detailed comparison has been established. Considering minimum mean-squared error decision feedback equalizer at the destination, a bound on the outage probability has been obtained for the antenna selection case and is used for comparisons. A cross-over point is observed while comparing the outage probabilities of equal-gain transmission and antenna selection techniques, as the signal-to-noise ratio increases and from that point antenna selection outperforms equal-gain transmission and this is explained by the fact of reduced residual self-interference in antenna selection method.
This thesis considers a full-duplex MIMO relay which amplifies and forwards the received signals, between a source and a destination that do not a have line of sight. Full-duplex mode raises the problem of self-interference. Though all the links in the system undergo frequency flat fading, the end-to-end effective channel is frequency selective. This is due to the imperfect cancellation of the self-interference at the relay and this residual self-interference acts as intersymbol interference at the destination which is treated by equalization. This also leads to complications in form of recursive equations to determine the input-output relationship of the system. This also leads to complications in the form of recursive equations to determine the input-output relationship of the system.
To overcome this, a signal flow graph approach using Mason's gain formula is proposed, where the effective channel is analyzed with keen notice to every loop and path the signal traverses. This gives a clear understanding and awareness about the orders of the polynomials involved in the transfer function, from which desired conclusions can be drawn. But the complexity of Mason's gain formula increases with the number of antennas at relay which can be overcome by the proposed linear algebraic method. Input-output relationship derived using simple concepts of linear algebra can be generalized to any number of antennas and the computation complexity is comparatively very low.
For a full-duplex amplify-and-forward MIMO relay system, assuming equalization at the destination, new mechanisms have been implemented at the relay that can compensate the effect of residual self-interference namely equal-gain transmission and antenna selection. Though equal-gain transmission does not perform better than the maximal ratio transmission, a trade-off can be made between performance and implementation complexity. Using the proposed antenna selection strategy, one pair of transmit-receive antennas at the relay is selected based on four selection criteria discussed. Outage probability analysis is performed for all the strategies presented and detailed comparison has been established. Considering minimum mean-squared error decision feedback equalizer at the destination, a bound on the outage probability has been obtained for the antenna selection case and is used for comparisons. A cross-over point is observed while comparing the outage probabilities of equal-gain transmission and antenna selection techniques, as the signal-to-noise ratio increases and from that point antenna selection outperforms equal-gain transmission and this is explained by the fact of reduced residual self-interference in antenna selection method.
ContributorsJonnalagadda, Geeta Sankar Kalyan (Author) / Tepedelenlioğlu, Cihan (Thesis advisor) / Bliss, Daniel (Committee member) / Kosut, Oliver (Committee member) / Arizona State University (Publisher)
Created2018
Description
This thesis presents a code generation tool to improve the programmability of systolic array processors such as the Domain Adaptive Processor (DAP) that was designed by researchers at the University of Michigan for wireless communication workloads. Unlike application-specific integrated circuits, DAP aims to achieve high performance without trading off much on programmability and reconfigurability. The structure of a typical DAP code for each Processing Element (PE) is very different from any other programming language format. As a result, writing code for DAP requires the programmer to acquire processor-specific knowledge including configuration rules, cycle accurate execution state for memory and datapath components within each PE, etc. Each code must be carefully handcrafted to meet the strict timing and resource constraints, leading to very long programming times and low productivity. In this thesis, a code generation and optimization tool is introduced to improve the programmability of DAP and make code development easier. The tool consists of a configuration code generator, optimizer, and a scheduler. An Instruction Set Architecture (ISA) has been designed specifically for DAP. The programmer writes the assembly code for each PE using the DAP ISA. The assembly code is then translated into a low-level configuration code. This configuration code undergoes several optimizations passes. Level 1 (L1) optimization handles instruction redundancy and performs loop optimizations through code movement. The Level 2 (L2) optimization performs instruction-level parallelism. Use of L1 and L2 optimization passes result in a code that has fewer instructions and requires fewer cycles. In addition, a scheduling tool has been introduced which performs final timing adjustments on the code to match the input data rate.
ContributorsVipperla, Anish (Author) / Chakrabarti, Chaitali (Thesis advisor) / Bliss, Daniel (Committee member) / Akoglu, Ali (Committee member) / Arizona State University (Publisher)
Created2022
Description
QR decomposition (QRD) of a matrix is one of the most common linear algebra operationsused for the decomposition of a square
on-square matrix. It has a wide range
of applications especially in Multiple Input-Multiple Output (MIMO) communication
systems. Unfortunately it has high computation complexity { for matrix size of nxn,
QRD has O(n3) complexity and back substitution, which is used to solve a system
of linear equations, has O(n2) complexity. Thus, as the matrix size increases, the
hardware resource requirement for QRD and back substitution increases signicantly.
This thesis presents the design and implementation of a
exible QRD and back substitution accelerator using a folded architecture. It can support matrix sizes of
4x4, 8x8, 12x12, 16x16, and 20x20 with low hardware resource requirement.
The proposed architecture is based on the systolic array implementation of the
Givens algorithm for QRD. It is built with three dierent types of computation blocks
which are connected in a 2-D array structure. These blocks are controlled by a
scheduler which facilitates reusability of the blocks to perform computation for any
input matrix size which is a multiple of 4. These blocks are designed using two
basic programming elements which support both the forward and backward paths to
compute matrix R in QRD and column-matrix X in back substitution computation.
The proposed architecture has been mapped to Xilinx Zynq Ultrascale+ FPGA
(Field Programmable Gate Array), ZCU102. All inputs are complex with precision
of 40 bits (38 fractional bits and 1 signed bit). The architecture can be clocked at
50 MHz. The synthesis results of the folded architecture for dierent matrix sizes
are presented. The results show that the folded architecture can support QRD and
back substitution for inputs of large sizes which otherwise cannot t on an FPGA
when implemented using a
at architecture. The memory sizes required for dierent
matrix sizes are also presented.
on-square matrix. It has a wide range
of applications especially in Multiple Input-Multiple Output (MIMO) communication
systems. Unfortunately it has high computation complexity { for matrix size of nxn,
QRD has O(n3) complexity and back substitution, which is used to solve a system
of linear equations, has O(n2) complexity. Thus, as the matrix size increases, the
hardware resource requirement for QRD and back substitution increases signicantly.
This thesis presents the design and implementation of a
exible QRD and back substitution accelerator using a folded architecture. It can support matrix sizes of
4x4, 8x8, 12x12, 16x16, and 20x20 with low hardware resource requirement.
The proposed architecture is based on the systolic array implementation of the
Givens algorithm for QRD. It is built with three dierent types of computation blocks
which are connected in a 2-D array structure. These blocks are controlled by a
scheduler which facilitates reusability of the blocks to perform computation for any
input matrix size which is a multiple of 4. These blocks are designed using two
basic programming elements which support both the forward and backward paths to
compute matrix R in QRD and column-matrix X in back substitution computation.
The proposed architecture has been mapped to Xilinx Zynq Ultrascale+ FPGA
(Field Programmable Gate Array), ZCU102. All inputs are complex with precision
of 40 bits (38 fractional bits and 1 signed bit). The architecture can be clocked at
50 MHz. The synthesis results of the folded architecture for dierent matrix sizes
are presented. The results show that the folded architecture can support QRD and
back substitution for inputs of large sizes which otherwise cannot t on an FPGA
when implemented using a
at architecture. The memory sizes required for dierent
matrix sizes are also presented.
ContributorsKanagala, Srimayee (Author) / Chakrabarti, Chaitali (Thesis advisor) / Bliss, Daniel (Committee member) / Cao, Yu (Kevin) (Committee member) / Arizona State University (Publisher)
Created2020
Description
The following document describes the hardware implementation and analysis of Temporal Interference Mitigation using High-Level Synthesis. As the problem of spectral congestion becomes more chronic and widespread, Electromagnetic radio frequency (RF) based systems are posing as viable solution to this problem. Among the existing RF methods Cooperation based systems have been a solution to a host of congestion problems. One of the most important elements of RF receiver is the spatially adaptive part of the receiver. Temporal Mitigation is vital technique employed at the receiver for signal recovery and future propagation along the radar chain.
The computationally intensive parts of temporal mitigation are identified and hardware accelerated. The hardware implementation is based on sequential approach with optimizations applied on the individual components for better performance.
An extensive analysis using a range of fixed point data types is performed to find the optimal data type necessary.
Finally a hybrid combination of data types for different components of temporal mitigation is proposed based on results from the above analysis.
The computationally intensive parts of temporal mitigation are identified and hardware accelerated. The hardware implementation is based on sequential approach with optimizations applied on the individual components for better performance.
An extensive analysis using a range of fixed point data types is performed to find the optimal data type necessary.
Finally a hybrid combination of data types for different components of temporal mitigation is proposed based on results from the above analysis.
ContributorsSiddiqui, Saquib Ahmad (Author) / Bliss, Daniel (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Ogras, Umit Y. (Committee member) / Jayasuriya, Suren (Committee member) / Arizona State University (Publisher)
Created2020