Matching Items (1,397)
Filtering by
- All Subjects: Chamber music
- Creators: ASU Library. Music Library
- Creators: Shrivastava, Aviral
ContributorsASU Library. Music Library (Publisher)
Created2018-04-09
Description
Ever reducing time to market, along with short product lifetimes, has created a need to shorten the microprocessor design time. Verification of the design and its analysis are two major components of this design cycle. Design validation techniques can be broadly classified into two major categories: simulation based approaches and formal techniques. Simulation based microprocessor validation involves running millions of cycles using random or pseudo random tests and allows verification of the register transfer level (RTL) model against an architectural model, i.e., that the processor executes instructions as required. The validation effort involves model checking to a high level description or simulation of the design against the RTL implementation. Formal techniques exhaustively analyze parts of the design but, do not verify RTL against the architecture specification. The focus of this work is to implement a fully automated validation environment for a MIPS based radiation hardened microprocessor using simulation based approaches. The basic framework uses the classical validation approach in which the design to be validated is described in a Hardware Definition Language (HDL) such as VHDL or Verilog. To implement a simulation based approach a number of random or pseudo random tests are generated. The output of the HDL based design is compared against the one obtained from a "perfect" model implementing similar functionality, a mismatch in the results would thus indicate a bug in the HDL based design. Effort is made to design the environment in such a manner that it can support validation during different stages of the design cycle. The validation environment includes appropriate changes so as to support architecture changes which are introduced because of radiation hardening. The manner in which the validation environment is build is highly dependent on the specifications of the perfect model used for comparisons. This work implements the validation environment for two MIPS simulators as the reference model. Two bugs have been discovered in the RTL model, using simulation based approaches through the validation environment.
ContributorsSharma, Abhishek (Author) / Clark, Lawrence (Thesis advisor) / Holbert, Keith E. (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2011
ContributorsJin, Leon (Performer) / Duo, Hongzuo (Performer) / Bergstedt, David (Performer) / Ellis, Gage (Performer) / Novak, Gail (Performer) / ASU Library. Music Library (Publisher)
Created2021-02-24
ContributorsWaters, Jared (Performer) / Creviston, Hannah (Performer) / Liu, Miao (Performer) / Guo, Hongzuo (Performer) / DeLaCruz, Nathaniel (Performer) / LoGuidice, Rosa (Performer) / Chiko, Ty (Performer) / Gatchel, David (Performer) / ASU Library. Music Library (Publisher)
Created2021-01-28
ContributorsKosminov, Vladislav (Performer) / Solari, John (Performer) / Liu, Shiyu (Performer) / Huang, Anruo (Performer) / Holly, Sean (Performer) / Novak, Gail (Performer) / Yang, Elliot (Performer) / Wu, Selene (Performer) / Kinnard, Zachariah (Performer) / Kuebelbeck, Stephen (Performer) / Johnson, Kaitlyn (Performer) / Bosworth, Robert (Performer) / Matejek, Ryan (Performer) / ASU Library. Music Library (Publisher)
Created2021-01-27
ContributorsSuehiro, Dylan (Conductor) / Kelley, Karen (Performer) / Ladley, Teddy (Performer) / ASU Library. Music Library (Publisher)
Created2021-04-19
Description
Performance improvements have largely followed Moore's Law due to the help from technology scaling. In order to continue improving performance, power-efficiency must be reduced. Better technology has improved power-efficiency, but this has a limit. Multi-core architectures have been shown to be an additional aid to this crusade of increased power-efficiency. Accelerators are growing in popularity as the next means of achieving power-efficient performance. Accelerators such as Intel SSE are ideal, but prove difficult to program. FPGAs, on the other hand, are less efficient due to their fine-grained reconfigurability. A middle ground is found in CGRAs, which are highly power-efficient, but largely programmable accelerators. Power-efficiencies of 100s of GOPs/W have been estimated, more than 2 orders of magnitude greater than current processors. Currently, CGRAs are limited in their applicability due to their ability to only accelerate a single thread at a time. This limitation becomes especially apparent as multi-core/multi-threaded processors have moved into the mainstream. This limitation is removed by enabling multi-threading on CGRAs through a software-oriented approach. The key capability in this solution is enabling quick run-time transformation of schedules to execute on targeted portions of the CGRA. This allows the CGRA to be shared among multiple threads simultaneously. Analysis shows that enabling multi-threading has very small costs but provides very large benefits (less than 1% single-threaded performance loss but nearly 300% CGRA throughput increase). By increasing dynamism of CGRA scheduling, system performance is shown to increase overall system performance of an optimized system by almost 350% over that of a single-threaded CGRA and nearly 20x faster than the same system with no CGRA in a highly threaded environment.
ContributorsPager, Jared (Author) / Shrivastava, Aviral (Thesis advisor) / Gupta, Sandeep (Committee member) / Speyer, Gil (Committee member) / Arizona State University (Publisher)
Created2011