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- All Subjects: Computer Engineering
- All Subjects: Overload Temperature
Description
Increasing computational demands in data centers require facilities to operate at higher ambient temperatures and at higher power densities. Conventionally, data centers are cooled with electrically-driven vapor-compressor equipment. This paper proposes an alternative data center cooling architecture that is heat-driven. The source is heat produced by the computer equipment. This dissertation details experiments investigating the quantity and quality of heat that can be captured from a liquid-cooled microprocessor on a computer server blade from a data center. The experiments involve four liquid-cooling setups and associated heat-extraction, including a radical approach using mineral oil. The trials examine the feasibility of using the thermal energy from a CPU to drive a cooling process. Uniquely, the investigation establishes an interesting and useful relationship simultaneously among CPU temperatures, power, and utilization levels. In response to the system data, this project explores the heat, temperature and power effects of adding insulation, varying water flow, CPU loading, and varying the cold plate-to-CPU clamping pressure. The idea is to provide an optimal and steady range of temperatures necessary for a chiller to operate. Results indicate an increasing relationship among CPU temperature, power and utilization. Since the dissipated heat can be captured and removed from the system for reuse elsewhere, the need for electricity-consuming computer fans is eliminated. Thermocouple readings of CPU temperatures as high as 93°C and a calculated CPU thermal energy up to 67Wth show a sufficiently high temperature and thermal energy to serve as the input temperature and heat medium input to an absorption chiller. This dissertation performs a detailed analysis of the exergy of a processor and determines the maximum amount of energy utilizable for work. Exergy as a source of realizable work is separated into its two contributing constituents: thermal exergy and informational exergy. The informational exergy is that usable form of work contained within the most fundamental unit of information output by a switching device within a CPU. Exergetic thermal, informational and efficiency values are calculated and plotted for our particular CPU, showing how the datasheet standards compare with experimental values. The dissertation concludes with a discussion of the work's significance.
ContributorsHaywood, Anna (Author) / Phelan, Patrick E (Thesis advisor) / Herrmann, Marcus (Committee member) / Gupta, Sandeep (Committee member) / Trimble, Steve (Committee member) / Myhajlenko, Stefan (Committee member) / Arizona State University (Publisher)
Created2014
Description
With the ever-increasing demand for high-end services, technological companies have been forced to operate on high performance servers. In addition to the customer services, the company's internal need to store and manage huge amounts of data has also increased their need to invest in High Density Data Centers. As a result, the performance to size of the data center has increased tremendously. Most of the consumed power by the servers is emitted as heat. In a High Density Data Center, the power per floor space area is higher compared to the regular data center. Hence the thermal management of this type of data center is relatively complicated.
Because of the very high power emission in a smaller containment, improper maintenance can result in failure of the data center operation in a shorter period. Hence the response time of the cooler to the temperature rise of the servers is very critical. Any delay in response will constantly lead to increased temperature and hence the server's failure.
In this paper, the significance of this delay time is understood by performing CFD simulation on different variants of High Density Modules using ANSYS Fluent. It was found out that the delay was becoming longer as the size of the data center increases. But the overload temperature, ie. the temperature rise beyond the set-point became lower with the increase in data center size. The results were common for both the single-row and the double-row model. The causes of the increased delay are accounted and explained in detail manner in this paper.
Because of the very high power emission in a smaller containment, improper maintenance can result in failure of the data center operation in a shorter period. Hence the response time of the cooler to the temperature rise of the servers is very critical. Any delay in response will constantly lead to increased temperature and hence the server's failure.
In this paper, the significance of this delay time is understood by performing CFD simulation on different variants of High Density Modules using ANSYS Fluent. It was found out that the delay was becoming longer as the size of the data center increases. But the overload temperature, ie. the temperature rise beyond the set-point became lower with the increase in data center size. The results were common for both the single-row and the double-row model. The causes of the increased delay are accounted and explained in detail manner in this paper.
ContributorsRamaraj, Dinesh Balaji (Author) / Gupta, Sandeep (Thesis advisor) / Hermann, Marcus (Committee member) / Huang, Huei-Ping (Committee member) / Arizona State University (Publisher)
Created2015
Description
Performance improvements have largely followed Moore's Law due to the help from technology scaling. In order to continue improving performance, power-efficiency must be reduced. Better technology has improved power-efficiency, but this has a limit. Multi-core architectures have been shown to be an additional aid to this crusade of increased power-efficiency. Accelerators are growing in popularity as the next means of achieving power-efficient performance. Accelerators such as Intel SSE are ideal, but prove difficult to program. FPGAs, on the other hand, are less efficient due to their fine-grained reconfigurability. A middle ground is found in CGRAs, which are highly power-efficient, but largely programmable accelerators. Power-efficiencies of 100s of GOPs/W have been estimated, more than 2 orders of magnitude greater than current processors. Currently, CGRAs are limited in their applicability due to their ability to only accelerate a single thread at a time. This limitation becomes especially apparent as multi-core/multi-threaded processors have moved into the mainstream. This limitation is removed by enabling multi-threading on CGRAs through a software-oriented approach. The key capability in this solution is enabling quick run-time transformation of schedules to execute on targeted portions of the CGRA. This allows the CGRA to be shared among multiple threads simultaneously. Analysis shows that enabling multi-threading has very small costs but provides very large benefits (less than 1% single-threaded performance loss but nearly 300% CGRA throughput increase). By increasing dynamism of CGRA scheduling, system performance is shown to increase overall system performance of an optimized system by almost 350% over that of a single-threaded CGRA and nearly 20x faster than the same system with no CGRA in a highly threaded environment.
ContributorsPager, Jared (Author) / Shrivastava, Aviral (Thesis advisor) / Gupta, Sandeep (Committee member) / Speyer, Gil (Committee member) / Arizona State University (Publisher)
Created2011