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- Creators: Barrett, The Honors College
- Resource Type: Text
Description
In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.
ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Created2013
Description
The purpose of this paper is to provide a new and improved design method for the Formula Society of Automotive Engineering (FSAE) team. There are five tasks that I accomplish in this paper: 1. I describe how the FSAE team is currently designing their car. This allows the reader to understand where the flaws might arise in their design method. 2. I then describe the key aspects of systems engineering design. This is the backbone of the method I am proposing, and it is important to understand the key concepts so that they can be applied to the FSAE design method. 3. I discuss what is available in the literature about race car design and optimization. I describe what other FSAE teams are doing and how that differs from systems engineering design. 4. I describe what the FSAE team at Arizona State University (ASU) should do to improve their approach to race car design. I go into detail about how the systems engineering method works and how it can and should be applied to the way they design their car. 5. I then describe how the team should implement this method because the method is useless if they do not implement it into their design process. I include an interview from their brakes team leader, Colin Twist, to give an example of their current method of design and show how it can be improved with the new method. This paper provides a framework for the FSAE team to develop their new method of design that will help them accomplish their overall goal of succeeding at the national competition.
ContributorsPickrell, Trevor Charles (Author) / Trimble, Steven (Thesis director) / Middleton, James (Committee member) / Barrett, The Honors College (Contributor) / Mechanical and Aerospace Engineering Program (Contributor)
Created2015-05
Description
The current Enterprise Requirements and Acquisition Model (ERAM), a discrete event simulation of the major tasks and decisions within the DoD acquisition system, identifies several what-if intervention strategies to improve program completion time. However, processes that contribute to the program acquisition completion time were not explicitly identified in the simulation study. This research seeks to determine the acquisition processes that contribute significantly to total simulated program time in the acquisition system for all programs reaching Milestone C. Specifically, this research examines the effect of increased scope management, technology maturity, and decreased variation and mean process times in post-Design Readiness Review contractor activities by performing additional simulation analyses. Potential policies are formulated from the results to further improve program acquisition completion time.
ContributorsWorger, Danielle Marie (Author) / Wu, Teresa (Thesis director) / Shunk, Dan (Committee member) / Wirthlin, J. Robert (Committee member) / Industrial, Systems (Contributor) / Barrett, The Honors College (Contributor)
Created2013-05
Description
Mission aviation groups operate aircraft in areas with limited infrastructure. Existing airdrop methods pose significant risk due to their lack of steerability. This thesis details the development of Manna, a system built to address these concerns. Manna provides an automated, low cost, safe steerable delivery platform, through a custom designed parafoil and guidance unit. Flight tests and simulations show that Manna can provide a safer alternative for critical air deliveries.
ContributorsSeveringhaus, Lukas (Author) / Schlichting, Audrey (Co-author) / Wende, Anthony (Thesis director) / Delp, Deana (Committee member) / Takahashi, Timothy (Committee member) / Barrett, The Honors College (Contributor) / Engineering Programs (Contributor)
Created2023-05