Matching Items (5)
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- All Subjects: Simultaneous Transmit and Receive Antennas
- Creators: Ozev, Sule
- Creators: Farahani, Bahar Jalali
- Resource Type: Text
Description
High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
ContributorsJankunas, Benjamin (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2014
Description
Semiconductor device scaling has kept up with Moore's law for the past decades and they have been scaling by a factor of half every one and half years. Every new generation of device technology opens up new opportunities and challenges and especially so for analog design. High speed and low gain is characteristic of these processes and hence a tradeoff that can enable to get back gain by trading speed is crucial. This thesis proposes a solution that increases the speed of sampling of a circuit by a factor of three while reducing the specifications on analog blocks and keeping the power nearly constant. The techniques are based on the switched capacitor technique called Correlated Level Shifting. A triple channel Cyclic ADC has been implemented, with each channel working at a sampling frequency of 3.33MS/s and a resolution of 14 bits. The specifications are compared with that based on a traditional architecture to show the superiority of the proposed technique.
ContributorsSivakumar, Balasubramanian (Author) / Farahani, Bahar Jalali (Thesis advisor) / Garrity, Douglas (Committee member) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2012
Description
The Built-In Self-Test for Simultaneous Transmit and Receive (BIST for STAR) will be able to solve the challenges of transmitting and receiving at the same time at the same frequency. One of the major components is the STAR antenna which transmits and receives along the same pathway. The main problem with doing both on the same path is that the transmit signal is usually much stronger in power compared to the received signal. The transmit signal has echoes and leakages that cause self-interference, preventing the received signal from being properly obtained. The solution developed in this project is the BIST component, which will help calculate the functional gain and phase offset of the interference signal and subtract it from the pathway so that the received signal remains. The functions of the proposed circuit board can be modeled in Matlab, where an emulation code generates a random, realistic functional gain and delay for the interference. From the generated values, the BIST for STAR was simulated to output what the measurements would be given the strength of the input signal and a controlled delay. The original Matlab code models an ideal environment directly recalculating the functional gain and phase from the given measurements in a second Matlab script. The actual product will not be ideal; a possible source of error to be considered is the effect of thermal noise. To observe the effect of noise on the BIST for STAR's performance, the Matlab code was expanded upon to include a component for thermal noise, and a method of analyzing the results of the board.
ContributorsLiu, Jennifer Yuan (Author) / Ozev, Sule (Thesis director) / Kozicki, Michael (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05
Description
The capstone portion of this project was to use the established STaR antennas and add a Built in Self-Test system to ensure the quality of the signals being received. This part of the project required a MatLab simulation to be built, a layout created, and a PCB designed for fabrication. In theory, the test BiST unit will allow the gain and delay of the transmitted signal and then cancel out unneeded interference for the received signal. However, this design required multiple paths to maintain the same lengths to keep the signals in phase for comparison. The purpose of this thesis is to show the potential drop-offs of the quality of the signals from being out of phase due to the wires that should be similar, being off by a certain percentage. This project will calculate the theoretical delay of all wires being out of sync and then add this delay to the established MatLab simulation. This report will show the relationship between the error of the received variables and what the actual generated values. And, the last part of the document will demonstrate the simulation by creating a signal and comparing it to its received counterpart. The end result of the study showed that the percent error between what is seen and what is expected is near insignificant and, hence, not an issue with regards to the quality of the project.
ContributorsSomers, Tyler Scott (Author) / Ozev, Sule (Thesis director) / Kozicki, Michael (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05
Description
The purpose of the Simultaneous Transmit and Receive Antenna project is to design a test circuit that will allow us to use an antenna to both send out and receive a signal at the same time on the same frequency. The test circuit will generate DC voltage levels that we can use to solve for the gain and delay of the transmit interference, so we will then be able to cancel out the unwanted signal from the received signal. With a theoretically perfect setup, the transmitted signal will be able to be completely isolated from the received signal, leaving us with only what we want at the output. In practice, however, this is not the case. There are many variables that will affect the integrity of the DC output of the test signal. As the output voltage level deviates from its theoretical perfect measurement, the precision to which we are able to solve for the gain and delay values decreases. The focus of this study is to estimate the effect of using a digital measurement tool to measure the output of the test circuit. Assuming a voltmeter with 1 volt full range, simulations were run using measurements stored at different bit resolutions, from 8-bit storage up to 16-bit storage. Since the physical hardware for the Simultaneous Transmit and Receive test circuit is not currently available, these tests were performed with an edited version of the Matlab simulation created for the Senior Design project. The simulation was run 2000 times over each bit resolution to get a wide range of generated values, then the error from each run was analyzed to come to a conclusion on the effect of the digital measurement on the design. The results of these simulations as well as further details of the project and testing are described inside this document.
ContributorsKral, Brandon Michael (Author) / Ozev, Sule (Thesis director) / Kozicki, Michael (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05