Matching Items (6)
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- All Subjects: Radio frequency integrated circuits
- All Subjects: Simultaneous Transmit and Receive Antennas
- Creators: Ozev, Sule
- Creators: Kral, Brandon Michael
- Creators: Somers, Tyler Scott
Description
Test cost has become a significant portion of device cost and a bottleneck in high volume manufacturing. Increasing integration density and shrinking feature sizes increased test time/cost and reduce observability. Test engineers have to put a tremendous effort in order to maintain test cost within an acceptable budget. Unfortunately, there is not a single straightforward solution to the problem. Products that are tested have several application domains and distinct customer profiles. Some products are required to operate for long periods of time while others are required to be low cost and optimized for low cost. Multitude of constraints and goals make it impossible to find a single solution that work for all cases. Hence, test development/optimization is typically design/circuit dependent and even process specific. Therefore, test optimization cannot be performed using a single test approach, but necessitates a diversity of approaches. This works aims at addressing test cost minimization and test quality improvement at various levels. In the first chapter of the work, we investigate pre-silicon strategies, such as design for test and pre-silicon statistical simulation optimization. In the second chapter, we investigate efficient post-silicon test strategies, such as adaptive test, adaptive multi-site test, outlier analysis, and process shift detection/tracking.
ContributorsYilmaz, Ender (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
Description
Built-in-Self-Test (BiST) for transmitters is a desirable choice since it eliminates the reliance on expensive instrumentation to do RF signal analysis. Existing on-chip resources, such as power or envelope detectors, or small additional circuitry can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as IQ imbalance, is challenging. In this work, a BiST technique to compute transmitter IQ imbalances using measurements out of a self-mixing envelope detector is proposed. Both the linear and non linear parameters of the RF transmitter path are extracted successfully. We first derive an analytical expression for the output signal. Using this expression, we devise test signals to isolate the effects of gain and phase imbalance, DC offsets, time skews and system nonlinearity from other parameters of the system. Once isolated, these parameters are calculated easily with a few mathematical operations. Simulations and hardware measurements show that the technique can provide accurate characterization of IQ imbalances. One of the glaring advantages of this method is that, the impairments are extracted from analyzing the response at baseband frequency and thereby eliminating the need of high frequency ATE (Automated Test Equipment).
ContributorsByregowda, Srinath (Author) / Ozev, Sule (Thesis advisor) / Cao, Yu (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
Description
Due to high level of integration in RF System on Chip (SOC), the test access points are limited to the baseband and RF inputs/outputs of the system. This limited access poses a big challenge particularly for advanced RF architectures where calibration of internal parameters is necessary and ensure proper operation. Therefore low-overhead built-in Self-Test (BIST) solution for advanced RF transceiver is proposed. In this dissertation. Firstly, comprehensive BIST solution for RF polar transceivers using on-chip resources is presented. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude (EVM). In the transmitter, delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion (IMD) that leads to violation of spectral mask requirements. Characterization and calibration of these parameters with analytical model would reduce the test time and cost considerably. Hence, a technique to measure and calibrate impairments of the polar transceiver in the loop-back mode is proposed.
Secondly, robust amplitude measurement technique for RF BIST application and BIST circuits for loop-back connection are discussed. Test techniques using analytical model are explained and BIST circuits are introduced.
Next, a self-compensating built-in self-test solution for RF Phased Array Mismatch is proposed. In the proposed method, a sinusoidal test signal with unknown amplitude is applied to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. In addition, proposed BIST system is designed and fabricated using IBM 180nm process and a prototype four-element phased-array PCB is also designed and fabricated for verifying the proposed method.
Finally, process independent gain measurement via BIST/DUT co-design is explained. Design methodology how to reduce performance impact significantly is discussed.
Simulation and hardware measurements results for the proposed techniques show that the proposed technique can characterize the targeted impairments accurately.
Secondly, robust amplitude measurement technique for RF BIST application and BIST circuits for loop-back connection are discussed. Test techniques using analytical model are explained and BIST circuits are introduced.
Next, a self-compensating built-in self-test solution for RF Phased Array Mismatch is proposed. In the proposed method, a sinusoidal test signal with unknown amplitude is applied to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. In addition, proposed BIST system is designed and fabricated using IBM 180nm process and a prototype four-element phased-array PCB is also designed and fabricated for verifying the proposed method.
Finally, process independent gain measurement via BIST/DUT co-design is explained. Design methodology how to reduce performance impact significantly is discussed.
Simulation and hardware measurements results for the proposed techniques show that the proposed technique can characterize the targeted impairments accurately.
ContributorsJeong, Jae Woong (Author) / Ozev, Sule (Thesis advisor) / Kitchen, Jennifer (Committee member) / Cao, Yu (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2015
Description
The Built-In Self-Test for Simultaneous Transmit and Receive (BIST for STAR) will be able to solve the challenges of transmitting and receiving at the same time at the same frequency. One of the major components is the STAR antenna which transmits and receives along the same pathway. The main problem with doing both on the same path is that the transmit signal is usually much stronger in power compared to the received signal. The transmit signal has echoes and leakages that cause self-interference, preventing the received signal from being properly obtained. The solution developed in this project is the BIST component, which will help calculate the functional gain and phase offset of the interference signal and subtract it from the pathway so that the received signal remains. The functions of the proposed circuit board can be modeled in Matlab, where an emulation code generates a random, realistic functional gain and delay for the interference. From the generated values, the BIST for STAR was simulated to output what the measurements would be given the strength of the input signal and a controlled delay. The original Matlab code models an ideal environment directly recalculating the functional gain and phase from the given measurements in a second Matlab script. The actual product will not be ideal; a possible source of error to be considered is the effect of thermal noise. To observe the effect of noise on the BIST for STAR's performance, the Matlab code was expanded upon to include a component for thermal noise, and a method of analyzing the results of the board.
ContributorsLiu, Jennifer Yuan (Author) / Ozev, Sule (Thesis director) / Kozicki, Michael (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05
Description
The capstone portion of this project was to use the established STaR antennas and add a Built in Self-Test system to ensure the quality of the signals being received. This part of the project required a MatLab simulation to be built, a layout created, and a PCB designed for fabrication. In theory, the test BiST unit will allow the gain and delay of the transmitted signal and then cancel out unneeded interference for the received signal. However, this design required multiple paths to maintain the same lengths to keep the signals in phase for comparison. The purpose of this thesis is to show the potential drop-offs of the quality of the signals from being out of phase due to the wires that should be similar, being off by a certain percentage. This project will calculate the theoretical delay of all wires being out of sync and then add this delay to the established MatLab simulation. This report will show the relationship between the error of the received variables and what the actual generated values. And, the last part of the document will demonstrate the simulation by creating a signal and comparing it to its received counterpart. The end result of the study showed that the percent error between what is seen and what is expected is near insignificant and, hence, not an issue with regards to the quality of the project.
ContributorsSomers, Tyler Scott (Author) / Ozev, Sule (Thesis director) / Kozicki, Michael (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05
Description
The purpose of the Simultaneous Transmit and Receive Antenna project is to design a test circuit that will allow us to use an antenna to both send out and receive a signal at the same time on the same frequency. The test circuit will generate DC voltage levels that we can use to solve for the gain and delay of the transmit interference, so we will then be able to cancel out the unwanted signal from the received signal. With a theoretically perfect setup, the transmitted signal will be able to be completely isolated from the received signal, leaving us with only what we want at the output. In practice, however, this is not the case. There are many variables that will affect the integrity of the DC output of the test signal. As the output voltage level deviates from its theoretical perfect measurement, the precision to which we are able to solve for the gain and delay values decreases. The focus of this study is to estimate the effect of using a digital measurement tool to measure the output of the test circuit. Assuming a voltmeter with 1 volt full range, simulations were run using measurements stored at different bit resolutions, from 8-bit storage up to 16-bit storage. Since the physical hardware for the Simultaneous Transmit and Receive test circuit is not currently available, these tests were performed with an edited version of the Matlab simulation created for the Senior Design project. The simulation was run 2000 times over each bit resolution to get a wide range of generated values, then the error from each run was analyzed to come to a conclusion on the effect of the digital measurement on the design. The results of these simulations as well as further details of the project and testing are described inside this document.
ContributorsKral, Brandon Michael (Author) / Ozev, Sule (Thesis director) / Kozicki, Michael (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05