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The flow of liquid PDMS (10:1 v/v base to cross-linker ratio) in open, rectangular silicon micro channels, with and without a hexa-methyl-di-silazane (HMDS) or poly-tetra-fluoro-ethylene (PTFE) (120 nm) coat, was studied. Photolithographic patterning and etching of silicon wafers was used to create micro channels with a range of widths (5-50

The flow of liquid PDMS (10:1 v/v base to cross-linker ratio) in open, rectangular silicon micro channels, with and without a hexa-methyl-di-silazane (HMDS) or poly-tetra-fluoro-ethylene (PTFE) (120 nm) coat, was studied. Photolithographic patterning and etching of silicon wafers was used to create micro channels with a range of widths (5-50 μm) and depths (5-20 μm). The experimental PDMS flow rates were compared to an analytical model based on the work of Lucas and Washburn. The experimental flow rates closely matched the predicted flow rates for channels with an aspect ratio (width to depth), p, between one and two. Flow rates in channels with p less than one were higher than predicted whereas the opposite was true for channels with p greater than two. The divergence between the experimental and predicted flow rates steadily increased with increasing p. These findings are rationalized in terms of the effect of channel dimensions on the front and top meniscus morphology and the possible deviation from the no-slip condition at the channel walls at high shear rates.

In addition, a preliminary experimental setup for calibration tests on ultrasensitive PDMS cantilever beams is reported. One loading and unloading cycle is completed on a microcantilever PDMS beam (theoretical stiffness 0.5 pN/ µm). Beam deflections are actuated by adjusting the buoyancy force on the beam, which is submerged in water, by the addition of heat. The expected loading and unloading curve is produced, albeit with significant noise. The experimental results indicate that the beam stiffness is a factor of six larger than predicted theoretically. One probable explanation is that the beam geometry may change when it is removed from the channel after curing, making assumptions about the beam geometry used in the theoretical analysis inaccurate. This theory is bolstered by experimental data discussed in the report. Other sources of error which could partially contribute to the divergent results are discussed. Improvements to the experimental setup for future work are suggested.
ContributorsSowers, Timothy Wayne (Author) / Rajagopalan, Jagannathan (Thesis advisor) / Herrmann, Marcus (Committee member) / Huang, Huei-Ping (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Increasing density of microelectronic packages, results in an increase in thermal and mechanical stresses within the various layers of the package. To accommodate the high-performance demands, the materials used in the electronic package would also require improvement. Specifically, the damage that often occurs in solders that function as die-attachment and

Increasing density of microelectronic packages, results in an increase in thermal and mechanical stresses within the various layers of the package. To accommodate the high-performance demands, the materials used in the electronic package would also require improvement. Specifically, the damage that often occurs in solders that function as die-attachment and thermal interfaces need to be addressed. This work evaluates and characterizes thermo-mechanical damage in two material systems – Electroplated Tin and Sintered Nano-Silver solder.

Tin plated electrical contacts are prone to formation of single crystalline tin whiskers which can cause short circuiting. A mechanistic model of their formation, evolution and microstructural influence is still not fully understood. In this work, growth of mechanically induced tin whiskers/hillocks is studied using in situ Nano-indentation and Electron Backscatter Diffraction (EBSD). Electroplated tin was indented and monitored in vacuum to study growth of hillocks without the influence of atmosphere. Thermal aging was done to study the effect of intermetallic compounds. Grain orientation of the hillocks and the plastically deformed region surrounding the indent was studied using Focused Ion Beam (FIB) lift-out technique. In addition, micropillars were milled on the surface of electroplated Sn using FIB to evaluate the yield strength and its relation to Sn grain size.

High operating temperature power electronics use wide band-gap semiconductor devices (Silicon Carbide/Gallium Nitride). The operating temperature of these devices can exceed 250oC, preventing use of traditional Sn-solders as Thermal Interface materials (TIM). At high temperature, the thermomechanical stresses can severely degrade the reliability and life of the device. In this light, new non-destructive approach is needed to understand the damage mechanism when subjected to reliability tests such as thermal cycling. In this work, sintered nano-Silver was identified as a promising high temperature TIM. Sintered nano-Silver samples were fabricated and their shear strength was evaluated. Thermal cycling tests were conducted and damage evolution was characterized using a lab scale 3D X-ray system to periodically assess changes in the microstructure such as cracks, voids, and porosity in the TIM layer. The evolution of microstructure and the effect of cycling temperature during thermal cycling are discussed.
ContributorsLujan Regalado, Irene (Author) / Chawla, Nikhilesh (Thesis advisor) / Frear, Darrel (Committee member) / Rajagopalan, Jagannathan (Committee member) / Jiao, Yang (Committee member) / Arizona State University (Publisher)
Created2018
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Description
Over the past several years, the density of integrated circuits has been increasing at a very fast rate, following Moore’s law. The advent of three dimensional (3D) packaging technologies enable the increase in density of integrated circuits without necessarily shrinking the dimensions of the device. Under such constraints, the solder

Over the past several years, the density of integrated circuits has been increasing at a very fast rate, following Moore’s law. The advent of three dimensional (3D) packaging technologies enable the increase in density of integrated circuits without necessarily shrinking the dimensions of the device. Under such constraints, the solder volume necessary to join the various layers of the package is also extremely small. At smaller length scales, the local cooling rates are higher, so the microstructures are much finer than that obtained in larger joints (BGA, C4). The fraction of intermetallic compounds (IMCs) present in solder joints in these volumes will be larger. The Cu6Sn5 precipitate size and spacing, and Sn grain structure and crystallography will be different at very small volumes. These factors will most certainly affect the performance of the solder. Examining the mechanical behavior and reliability of Pb-free solders is difficult, primarily because a methodology to characterize the microstructure and the mechanics of deformation at these extremely small length scales has yet to be developed.

In this study, Sn grain orientation and Cu6Sn5 IMC fraction, size, and morphology are characterized in 3D, in pure Sn based solder joints. The obtained results show differences in morphology of Sn grains and IMC precipitates as a function of location within the solder joint indicating influence of local cooling rate differences. Ex situ and in situ electromigration tests done on 250 um and 500 um pure Sn solder joints elucidate the evolution of microstructure, specifically Sn grain growth, IMC segregation and surface degradation. This research implements 3D quantification of microstructural features over micro and nano-scales, thereby enabling a multi-scale / multi-characterization approach.
ContributorsKirubanandham, Antony (Author) / Chawla, Nikhilesh (Thesis advisor) / Jiao, Yang (Committee member) / Lu, Minhua (Committee member) / Rajagopalan, Jagannathan (Committee member) / Arizona State University (Publisher)
Created2016