Matching Items (9)
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- All Subjects: Metal oxide semiconductors, Complementary
- Creators: Bakkaloglu, Bertan
- Creators: Holgate, Matthew
- Member of: Theses and Dissertations
Description
Memories play an integral role in today's advanced ICs. Technology scaling has enabled high density designs at the price paid for impact due to variability and reliability. It is imperative to have accurate methods to measure and extract the variability in the SRAM cell to produce accurate reliability projections for future technologies. This work presents a novel test measurement and extraction technique which is non-invasive to the actual operation of the SRAM memory array. The salient features of this work include i) A single ended SRAM test structure with no disturbance to SRAM operations ii) a convenient test procedure that only requires quasi-static control of external voltages iii) non-iterative method that extracts the VTH variation of each transistor from eight independent switch point measurements. With the present day technology scaling, in addition to the variability with the process, there is also the impact of other aging mechanisms which become dominant. The various aging mechanisms like Negative Bias Temperature Instability (NBTI), Channel Hot Carrier (CHC) and Time Dependent Dielectric Breakdown (TDDB) are critical in the present day nano-scale technology nodes. In this work, we focus on the impact of NBTI due to aging in the SRAM cell and have used Trapping/De-Trapping theory based log(t) model to explain the shift in threshold voltage VTH. The aging section focuses on the following i) Impact of Statistical aging in PMOS device due to NBTI dominates the temporal shift of SRAM cell ii) Besides static variations , shifting in VTH demands increased guard-banding margins in design stage iii) Aging statistics remain constant during the shift, presenting a secondary effect in aging prediction. iv) We have investigated to see if the aging mechanism can be used as a compensation technique to reduce mismatch due to process variations. Finally, the entire test setup has been tested in SPICE and also validated with silicon and the results are presented. The method also facilitates the study of design metrics such as static, read and write noise margins and also the data retention voltage and thus help designers to improve the cell stability of SRAM.
ContributorsRavi, Venkatesa (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Clark, Lawrence (Committee member) / Arizona State University (Publisher)
Created2013
Description
The aging process due to Bias Temperature Instability (both NBTI and PBTI) and Channel Hot Carrier (CHC) is a key limiting factor of circuit lifetime in CMOS design. Threshold voltage shift due to BTI is a strong function of stress voltage and temperature complicating stress and recovery prediction. This poses a unique challenge for long-term aging prediction for wide range of stress patterns. Traditional approaches usually resort to an average stress waveform to simplify the lifetime prediction. They are efficient, but fail to capture circuit operation, especially under dynamic voltage scaling (DVS) or in analog/mixed signal designs where the stress waveform is much more random. This work presents a suite of modelling solutions for BTI that enable aging simulation under all possible stress conditions. Key features of this work are compact models to predict BTI aging based on Reaction-Diffusion theory when the stress voltage is varying. The results to both reaction-diffusion (RD) and trapping-detrapping (TD) mechanisms are presented to cover underlying physics. Silicon validation of these models is performed at 28nm, 45nm and 65nm technology nodes, at both device and circuit levels. Efficient simulation leveraging the BTI models under DVS and random input waveform is applied to both digital and analog representative circuits such as ring oscillators and LNA. Both physical mechanisms are combined into a unified model which improves prediction accuracy at 45nm and 65nm nodes. Critical failure condition is also illustrated based on NBTI and PBTI at 28nm. A comprehensive picture for duty cycle shift is shown. DC stress under clock gating schemes results in monotonic shift in duty cycle which an AC stress causes duty cycle to converge close to 50% value. Proposed work provides a general and comprehensive solution to aging analysis under random stress patterns under BTI.
Channel hot carrier (CHC) is another dominant degradation mechanism which affects analog and mixed signal circuits (AMS) as transistor operates continuously in saturation condition. New model is proposed to account for e-e scattering in advanced technology nodes due to high gate electric field. The model is validated with 28nm and 65nm thick oxide data for different stress voltages. It demonstrates shift in worst case CHC condition to Vgs=Vds from Vgs=0.5Vds. A novel iteration based aging simulation framework for AMS designs is proposed which eliminates limitation for conventional reliability tools. This approach helps us identify a unique positive feedback mechanism termed as Bias Runaway. Bias runaway, is rapid increase of the bias voltage in AMS circuits which occurs when the feedback between the bias current and the effect of channel hot carrier turns into positive. The degradation of CHC is a gradual process but under specific circumstances, the degradation rate can be dramatically accelerated. Such a catastrophic phenomenon is highly sensitive to the initial operation condition, as well as transistor gate length. Based on 65nm silicon data, our work investigates the critical condition that triggers bias runaway, and the impact of gate length tuning. We develop new compact models as well as the simulation methodology for circuit diagnosis, and propose design solutions and the trade-offs to avoid bias runaway, which is vitally important to reliable AMS designs.
Channel hot carrier (CHC) is another dominant degradation mechanism which affects analog and mixed signal circuits (AMS) as transistor operates continuously in saturation condition. New model is proposed to account for e-e scattering in advanced technology nodes due to high gate electric field. The model is validated with 28nm and 65nm thick oxide data for different stress voltages. It demonstrates shift in worst case CHC condition to Vgs=Vds from Vgs=0.5Vds. A novel iteration based aging simulation framework for AMS designs is proposed which eliminates limitation for conventional reliability tools. This approach helps us identify a unique positive feedback mechanism termed as Bias Runaway. Bias runaway, is rapid increase of the bias voltage in AMS circuits which occurs when the feedback between the bias current and the effect of channel hot carrier turns into positive. The degradation of CHC is a gradual process but under specific circumstances, the degradation rate can be dramatically accelerated. Such a catastrophic phenomenon is highly sensitive to the initial operation condition, as well as transistor gate length. Based on 65nm silicon data, our work investigates the critical condition that triggers bias runaway, and the impact of gate length tuning. We develop new compact models as well as the simulation methodology for circuit diagnosis, and propose design solutions and the trade-offs to avoid bias runaway, which is vitally important to reliable AMS designs.
ContributorsSutaria, Ketul (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Chakrabarti, Chaitali (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Created2014
Description
Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
ContributorsPadala, Sudheer (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
Many industries require workers in warehouse and stockroom environments to perform frequent lifting tasks. Over time these repeated tasks can lead to excess strain on the worker's body and reduced productivity. This project seeks to develop an exoskeletal wrist fixture to be used in conjunction with a powered exoskeleton arm to aid workers performing box lifting types of tasks. Existing products aimed at improving worker comfort and productivity typically employ either fully powered exoskeleton suits or utilize minimally powered spring arms and/or fixtures. These designs either reduce stress to the user's body through powered arms and grippers operated via handheld controls which have limited functionality, or they use a more minimal setup that reduces some load, but exposes the user's hands and wrists to injury by directing support to the forearm. The design proposed here seeks to strike a balance between size, weight, and power requirements and also proposes a novel wrist exoskeleton design which minimizes stress on the user's wrists by directly interfacing with the object to be picked up. The design of the wrist exoskeleton was approached through initially selecting degrees of freedom and a ROM (range of motion) to accommodate. Feel and functionality were improved through an iterative prototyping process which yielded two primary designs. A novel "clip-in" method was proposed to allow the user to easily attach and detach from the exoskeleton. Designs utilized a contact surface intended to be used with dry fibrillary adhesives to maximize exoskeleton grip. Two final designs, which used two pivots in opposite kinematic order, were constructed and tested to determine the best kinematic layout. The best design had two prototypes created to be worn with passive test arms that attached to the user though a specially designed belt.
ContributorsGreason, Kenneth Berend (Author) / Sugar, Thomas (Thesis director) / Holgate, Matthew (Committee member) / Mechanical and Aerospace Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-12
Description
In order for assistive mobile robots to operate in the same environment as humans, they must be able to navigate the same obstacles as humans do. Many elements are required to do this: a powerful controller which can understand the obstacle, and power-dense actuators which will be able to achieve the necessary limb accelerations and output energies. Rapid growth in information technology has made complex controllers, and the devices which run them considerably light and cheap. The energy density of batteries, motors, and engines has not grown nearly as fast. This is problematic because biological systems are more agile, and more efficient than robotic systems. This dissertation introduces design methods which may be used optimize a multiactuator robotic limb's natural dynamics in an effort to reduce energy waste. These energy savings decrease the robot's cost of transport, and the weight of the required fuel storage system. To achieve this, an optimal design method, which allows the specialization of robot geometry, is introduced. In addition to optimal geometry design, a gearing optimization is presented which selects a gear ratio which minimizes the electrical power at the motor while considering the constraints of the motor. Furthermore, an efficient algorithm for the optimization of parallel stiffness elements in the robot is introduced. In addition to the optimal design tools introduced, the KiTy SP robotic limb structure is also presented. Which is a novel hybrid parallel-serial actuation method. This novel leg structure has many desirable attributes such as: three dimensional end-effector positioning, low mobile mass, compact form-factor, and a large workspace. We also show that the KiTy SP structure outperforms the classical, biologically-inspired serial limb structure.
ContributorsCahill, Nathan M (Author) / Sugar, Thomas (Thesis advisor) / Ren, Yi (Thesis advisor) / Holgate, Matthew (Committee member) / Berman, Spring (Committee member) / Artemiadis, Panagiotis (Committee member) / Arizona State University (Publisher)
Created2017
Description
The market for high speed camera chips, or image sensors, has experienced rapid growth over the past decades owing to its broad application space in security, biomedical equipment, and mobile devices. CMOS (complementary metal-oxide-semiconductor) technology has significantly improved the performance of the high speed camera chip by enabling the monolithic integration of pixel circuits and on-chip analog-to-digital conversion. However, for low light intensity applications, many CMOS image sensors have a sub-optimum dynamic range, particularly in high speed operation. Thus the requirements for a sensor to have a high frame rate and high fill factor is attracting more attention. Another drawback for the high speed camera chip is its high power demands due to its high operating frequency. Therefore, a CMOS image sensor with high frame rate, high fill factor, high voltage range and low power is difficult to realize.
This thesis presents the design of pixel circuit, the pixel array and column readout chain for a high speed camera chip. An integrated PN (positive-negative) junction photodiode and an accompanying ten transistor pixel circuit are implemented using a 0.18 µm CMOS technology. Multiple methods are applied to minimize the subthreshold currents, which is critical for low light detection. A layout sharing technique is used to increase the fill factor to 64.63%. Four programmable gain amplifiers (PGAs) and 10-bit pipeline analog-to-digital converters (ADCs) are added to complete on-chip analog to digital conversion. The simulation results of extracted circuit indicate ENOB (effective number of bits) is greater than 8 bits with FoM (figures of merit) =0.789. The minimum detectable voltage level is determined to be 470μV based on noise analysis. The total power consumption of PGA and ADC is 8.2mW for each conversion. The whole camera chip reaches 10508 frames per second (fps) at full resolution with 3.1mm x 3.4mm area.
This thesis presents the design of pixel circuit, the pixel array and column readout chain for a high speed camera chip. An integrated PN (positive-negative) junction photodiode and an accompanying ten transistor pixel circuit are implemented using a 0.18 µm CMOS technology. Multiple methods are applied to minimize the subthreshold currents, which is critical for low light detection. A layout sharing technique is used to increase the fill factor to 64.63%. Four programmable gain amplifiers (PGAs) and 10-bit pipeline analog-to-digital converters (ADCs) are added to complete on-chip analog to digital conversion. The simulation results of extracted circuit indicate ENOB (effective number of bits) is greater than 8 bits with FoM (figures of merit) =0.789. The minimum detectable voltage level is determined to be 470μV based on noise analysis. The total power consumption of PGA and ADC is 8.2mW for each conversion. The whole camera chip reaches 10508 frames per second (fps) at full resolution with 3.1mm x 3.4mm area.
ContributorsZhao, Tong (Author) / Barnaby, Hugh (Thesis advisor) / Mikkola, Esko (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2017
Description
This thesis presents a gas sensor readout IC for amperometric and conductometric electrochemical sensors. The Analog Front-End (AFE) readout circuit enables tracking long term exposure to hazardous gas fumes in diesel and gasoline equipments, which may be correlated to diseases. Thus, the detection and discrimination of gases using microelectronic gas sensor system is required. This thesis describes the research, development, implementation and test of a small and portable based prototype platform for chemical gas sensors to enable a low-power and low noise gas detection system. The AFE reads out the outputs of eight conductometric sensor array and eight amperometric sensor arrays. The IC consists of a low noise potentiostat, and associated 9bit current-steering DAC for sensor stimulus, followed by the first order nested chopped £U£G ADC. The conductometric sensor uses a current driven approach for extracting conductance of the sensor depending on gas concentration. The amperometric sensor uses a potentiostat to apply constant voltage to the sensors and an I/V converter to measure current out of the sensor. The core area for the AFE is 2.65x0.95 mm2. The proposed system achieves 91 dB SNR at 1.32 mW quiescent power consumption per channel. With digital offset storage and nested chopping, the readout chain achieves 500 fÝV input referred offset.
ContributorsKim, Hyun-Tae (Author) / Bakkaloglu, Bertan (Thesis advisor) / Vermeire, Bert (Committee member) / Spanias, Andreas (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2011
Description
Rail clamp circuits are widely used for electrostatic discharge (ESD) protection in semiconductor products today. A step-by-step design procedure for the traditional RC and single-inverter-based rail clamp circuit and the design, simulation, implementation, and operation of two novel rail clamp circuits are described for use in the ESD protection of complementary metal-oxide-semiconductor (CMOS) circuits. The step-by-step design procedure for the traditional circuit is technology-node independent, can be fully automated, and aims to achieve a minimal area design that meets specified leakage and ESD specifications under all valid process, voltage, and temperature (PVT) conditions. The first novel rail clamp circuit presented employs a comparator inside the traditional circuit to reduce the value of the time constant needed. The second circuit uses a dynamic time constant approach in which the value of the time constant is dynamically adjusted after the clamp is triggered. Important metrics for the two new circuits such as ESD performance, latch-on immunity, clamp recovery time, supply noise immunity, fastest power-on time supported, and area are evaluated over an industry-standard PVT space using SPICE simulations and measurements on a fabricated 40 nm test chip.
ContributorsVenkatasubramanian, Ramachandran (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2016
Description
This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below:
1) A transformer-based power combiner architecture for out-phasing transmitters
2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)
3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters
This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.
The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.
Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.
1) A transformer-based power combiner architecture for out-phasing transmitters
2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)
3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters
This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.
The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.
Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.
ContributorsMoallemi, Soroush (Author) / Kitchen, Jennifer (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2019