Matching Items (5)
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- All Subjects: Gallium Nitride
- Creators: Kitchen, Jennifer
- Creators: Kumar, Viswanathan Naveen
- Status: Published
Description
Semiconductor nanowires have the potential to emerge as the building blocks of next generation field-effect transistors, logic gates, solar cells and light emitting diodes. Use of Gallium Nitride (GaN) and other wide bandgap materials combines the advantages of III-nitrides along with the enhanced mobility offered by 2-dimensional confinement present in nanowires. The focus of this thesis is on developing a low field mobility model for a GaN nanowire using Ensemble Monte Carlo (EMC) techniques. A 2D Schrödinger-Poisson solver and a one-dimensional Monte Carlo solver is developed for an Aluminum Gallium Nitride/Gallium Nitride Heterostructure nanowire. A GaN/AlN/AlGaN heterostructure device is designed which creates 2-dimensional potential well for electrons. The nanowire is treated as a quasi-1D system in this work. A self-consistent 2D Schrödinger-Poisson solver is designed which determines the subband energies and the corresponding wavefunctions of the confined system. Three scattering mechanisms: acoustic phonon scattering, polar optical phonon scattering and piezoelectric scattering are considered to account for the electron phonon interactions in the system. Overlap integrals and 1D scattering rate expressions are derived for all the mechanisms listed. A generic one-dimensional Monte Carlo solver is also developed. Steady state results from the 1D Monte Carlo solver are extracted to determine the low field mobility of the GaN nanowires.
ContributorsKumar, Viswanathan Naveen (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Zhao, Yuji (Committee member) / Arizona State University (Publisher)
Created2017
Description
Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing.
This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor.
Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.
This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor.
Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.
ContributorsHegde, Ashwath (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2018
Description
In competitive Taekwondo, Electronic Body Protectors (EBPs) are used to register hits made by players during sparring. EBPs are comprised of three main components: chest guard, foot sock, and headgear. This equipment interacts with each other through the use of magnets, electric sensors, transmitters, and a receiver. The receiver is connected to a computer programmed with software to process signals from the transmitter and determine whether or not a competitor scored a point. The current design of EBPs, however, have numerous shortcomings, including sensing false positives, failing to register hits, costing too much, and relying on human judgment. This thesis will thoroughly delineate the operation of the current EBPs used and discuss research performed in order to eliminate these weaknesses.
ContributorsSpell, Valerie Anne (Author) / Kozicki, Michael (Thesis director) / Kitchen, Jennifer (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05
Description
This paper reviews several current designs of Cube Satellite (CubeSat) Electrical Power Systems (EPS) based on Silicon FET technologies and their current deficiencies, such as radiation-incurred defects and switching power losses. A strategy to fix these is proposed by the way of using Gallium Nitride (GaN) High Electron-Mobility Transistors (HEMTs) as switching devices within Buck/Boost Converters and other regulators. This work summarizes the EPS designs of several CubeSat missions, classifies them, and outlines their efficiency. An in-depth example of an EPS is also given, explaining the process in which these systems are designed. Areas of deficiency are explained along with reasoning as to why GaN can mitigate these losses, including its wide bandgap properties such as high RDS(on) and High Breakdown Voltage. Special design considerations must be kept in mind when using GaN HEMTs in this application and an example of a CubeSat using GaN HEMTs is mentioned. Finally, challenges ahead for GaN are explored including manufacturing considerations and long-term reliability.
ContributorsWilloughby, Alexander George (Author) / Kitchen, Jennifer (Thesis director) / Zhao, Yuji (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2017-05
Description
Gallium Nitride (GaN) is uniquely suited for Radio Frequency (RF) and power electronic applications due to its intrinsically high saturation velocity and high mobility compared to Silicon and Silicon Carbide (SiC). High Electron Mobility Transistors (HEMTs) have remained the primary topology for GaN transistors in RF applications. However, GaN HEMTs suffer from a variety of issues such as current crowding, lack of enhancement mode (E-Mode) operation and non-linearity. These drawbacks slow the widespread adoption of GaN devices for ultra-low voltage (ULV) applications such as voltage regulators, automotive and computing applications. E-mode operation is especially desired in low-voltage high frequency switching applications. In this context, Fin Field Effect Transistors (FinFETs) offer an alternative topology for ULV applications as opposed to conventional HEMTs. Recent advances in material processing, high aspect ratio epitaxial growth and etching methods has led to an increased interest in 3D nanostructures such as Nano-FinFETs and Nanowire FETs. A typical 3D nano-FinFET is the AlGaN/GaN Metal Insulator Semiconductor (MIS) FET wherein a layer of Al2O3 surrounds the AlGaN/GaN fin. The presence of the side gates leads to additional lateral confinement of the 2D Electron Gas (2DEG). Theoretical calculations of transport properties in confined systems such as AlGaN/GaN Finfets are scarce compared to those of their planar HEMT counterparts.
A novel simulator is presented in this dissertation, which employs self-consistent solution of the coupled 1D Boltzmann – 2D Schrödinger – 3D Poisson problem, to yield the channel electrostatics and the low electric field transport characteristics of AlGaN/GaN MIS FinFETs. The low field electron mobility is determined by solving the Boltzmann transport equation in the Quasi-1D region using 1D Ensemble Monte Carlo method. Three electron-phonon scattering mechanisms (acoustic, piezoelectric and polar optical phonon scattering) and interface roughness scattering at the AlGaN/GaN interface are considered in this theoretical model. Simulated low-field electron mobility and its temperature dependence are in agreement with experimental data reported in the literature.
A quasi-1D version of alloy clustering model is derived and implemented and the limiting effect of alloy clustering on the low-field electron mobility is investigated for the first time for MIS FinFET device structures.
ContributorsKumar, Viswanathan Naveen (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Nemanich, Robert (Committee member) / Povolotskyi, Michael (Committee member) / Esqueda, Ivan Sanchez (Committee member) / Arizona State University (Publisher)
Created2022