Matching Items (5)
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- All Subjects: Electrical
- Creators: Ozev, Sule
- Creators: Aberle, James T., 1961-
- Creators: Nekkalapu, Sameer
Description
High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
ContributorsJankunas, Benjamin (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2014
Description
Semiconductor device scaling has kept up with Moore's law for the past decades and they have been scaling by a factor of half every one and half years. Every new generation of device technology opens up new opportunities and challenges and especially so for analog design. High speed and low gain is characteristic of these processes and hence a tradeoff that can enable to get back gain by trading speed is crucial. This thesis proposes a solution that increases the speed of sampling of a circuit by a factor of three while reducing the specifications on analog blocks and keeping the power nearly constant. The techniques are based on the switched capacitor technique called Correlated Level Shifting. A triple channel Cyclic ADC has been implemented, with each channel working at a sampling frequency of 3.33MS/s and a resolution of 14 bits. The specifications are compared with that based on a traditional architecture to show the superiority of the proposed technique.
ContributorsSivakumar, Balasubramanian (Author) / Farahani, Bahar Jalali (Thesis advisor) / Garrity, Douglas (Committee member) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2012
Description
Until late 1970’s the primary focus in power system modeling has been largely directed towards power system generation and transmission. Over the years, the importance of load modeling grew and having an accurate representation of load played an important role in the planning and operation studies. With an emphasis on tackling the topic of load modeling, this thesis presents the following intermediary steps in developing accurate load models:
1. Synthesis of a three-phase standard feeder and load model using the measured voltages and currents, for events such as faults and feeder pickup cases, obtained at the head of the feeder.
2. Investigated the impact of the synthesized standard feeder and load model on the sub-transmission system for a feeder pick-up case.
In the first phase of this project, a standard feeder and load model had been synthesized by capturing the current transients when three-phase voltage measurements (obtained from a local electric utility) are played-in as input to the synthesized model. The comparison between the measured currents and the simulated currents obtained using an electromagnetic transient analysis software (PSCAD) are made at the head of the designed feeder. The synthesized load model has a load composition which includes impedance loads, single-phase induction motor loads and three-phase induction motor loads. The parameters of the motor models are adjusted to obtain a good correspondence between measured three-phase currents and simulated current responses at the head of the feeder when subjected to events under which measurements were obtained on the feeder. These events include faults which occurred upstream of the feeder at a higher voltage level and a feeder pickup event that occurred downstream from the head of the feeder. Two different load compositions have been obtained for this feeder and load model depending on the types of load present in the surrounding area (residential or industrial/commercial).
The second phase of this project examines the impact of the feeder pick-up event on the 69 kV sub-transmission system using the obtained standard feeder and load model. Using the 69 kV network data obtained from a local utility, a sub-transmission network has been built in PSCAD. The main difference between the first and second phase of this project is that no measurements are played-in to the model in the latter case. Instead, the feeder pick-up event at a particular substation is simulated using the reduced equivalent of the 69 kV sub-transmission circuit together with the synthesized three-phase models of the feeder and the loads obtained in the first phase of the project. Using this analysis, it is observed that a good correspondence between the PSCAD simulated values of both three-phase voltages and currents with their corresponding measured responses at the substation is achieved.
1. Synthesis of a three-phase standard feeder and load model using the measured voltages and currents, for events such as faults and feeder pickup cases, obtained at the head of the feeder.
2. Investigated the impact of the synthesized standard feeder and load model on the sub-transmission system for a feeder pick-up case.
In the first phase of this project, a standard feeder and load model had been synthesized by capturing the current transients when three-phase voltage measurements (obtained from a local electric utility) are played-in as input to the synthesized model. The comparison between the measured currents and the simulated currents obtained using an electromagnetic transient analysis software (PSCAD) are made at the head of the designed feeder. The synthesized load model has a load composition which includes impedance loads, single-phase induction motor loads and three-phase induction motor loads. The parameters of the motor models are adjusted to obtain a good correspondence between measured three-phase currents and simulated current responses at the head of the feeder when subjected to events under which measurements were obtained on the feeder. These events include faults which occurred upstream of the feeder at a higher voltage level and a feeder pickup event that occurred downstream from the head of the feeder. Two different load compositions have been obtained for this feeder and load model depending on the types of load present in the surrounding area (residential or industrial/commercial).
The second phase of this project examines the impact of the feeder pick-up event on the 69 kV sub-transmission system using the obtained standard feeder and load model. Using the 69 kV network data obtained from a local utility, a sub-transmission network has been built in PSCAD. The main difference between the first and second phase of this project is that no measurements are played-in to the model in the latter case. Instead, the feeder pick-up event at a particular substation is simulated using the reduced equivalent of the 69 kV sub-transmission circuit together with the synthesized three-phase models of the feeder and the loads obtained in the first phase of the project. Using this analysis, it is observed that a good correspondence between the PSCAD simulated values of both three-phase voltages and currents with their corresponding measured responses at the substation is achieved.
ContributorsNekkalapu, Sameer (Author) / Vittal, Vijay (Thesis advisor) / Undrill, John M (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2018
Description
Testing and calibration constitute a significant part of the overall manufacturing cost of microelectromechanical system (MEMS) devices. Developing a low-cost testing and calibration scheme applicable at the user side that ensures the continuous reliability and accuracy is a crucial need. The main purpose of testing is to eliminate defective devices and to verify the qualifications of a product is met. The calibration process for capacitive MEMS devices, for the most part, entails the determination of the mechanical sensitivity. In this work, a physical-stimulus-free built-in-self-test (BIST) integrated circuit (IC) design characterizing the sensitivity of capacitive MEMS accelerometers is presented. The BIST circuity can extract the amplitude and phase response of the acceleration sensor's mechanics under electrical excitation within 0.55% of error with respect to its mechanical sensitivity under the physical stimulus. Sensitivity characterization is performed using a low computation complexity multivariate linear regression model. The BIST circuitry maximizes the use of existing analog and mixed-signal readout signal chain and the host processor core, without the need for computationally expensive Fast Fourier Transform (FFT)-based approaches. The BIST IC is designed and fabricated using the 0.18-µm CMOS technology. The sensor analog front-end and BIST circuitry are integrated with a three-axis, low-g capacitive MEMS accelerometer in a single hermetically sealed package. The BIST circuitry occupies 0.3 mm2 with a total readout IC area of 1.0 mm2 and consumes 8.9 mW during self-test operation.
ContributorsOzel, Muhlis Kenan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2017
Description
Micro Electro Mechanical Systems (MEMS) based accelerometers are one of the most commonly used sensors out there. They are used in devices such as, airbags, smartphones, airplanes, and many more. Although they are very accurate, they degrade with time or get offset due to some damage. To fix this, they must be calibrated again using physical calibration technique, which is an expensive process to conduct. However, these sensors can also be calibrated infield by applying an on-chip electrical stimulus to the sensor. Electrical stimulus-based calibration could bring the cost of testing and calibration significantly down as compared to factory testing. In this thesis, simulations are presented to formulate a statistical prediction model based on an electrical stimulus. Results from two different approaches of electrical calibration have been discussed. A prediction model with a root mean square error of 1% has been presented in this work. Experiments were conducted on commercially available accelerometers to test the techniques used for simulations.
ContributorsBassi, Ishaan (Author) / Ozev, Sule (Thesis advisor) / Christen, Jennifer Blain (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2020