Matching Items (6)
Filtering by
- Creators: Arizona State University
- Creators: Ozev, Sule
Description
Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased efficiency, but at the cost of distortion. Class AB amplifiers have low efficiency, but high linearity. By modulating the supply voltage of a Class AB amplifier to make a Class H amplifier, the efficiency can increase while still maintaining the Class AB level of linearity. A 92dB Power Supply Rejection Ratio (PSRR) Class AB amplifier and a Class H amplifier were designed in a 0.24um process for portable audio applications. Using a multiphase buck converter increased the efficiency of the Class H amplifier while still maintaining a fast response time to respond to audio frequencies. The Class H amplifier had an efficiency above the Class AB amplifier by 5-7% from 5-30mW of output power without affecting the total harmonic distortion (THD) at the design specifications. The Class H amplifier design met all design specifications and showed performance comparable to the designed Class AB amplifier across 1kHz-20kHz and 0.01mW-30mW. The Class H design was able to output 30mW into 16Ohms without any increase in THD. This design shows that Class H amplifiers merit more research into their potential for increasing efficiency of audio amplifiers and that even simple designs can give significant increases in efficiency without compromising linearity.
ContributorsPeterson, Cory (Author) / Bakkaloglu, Bertan (Thesis advisor) / Barnaby, Hugh (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
Description
Class D Amplifiers are widely used in portable systems such as mobile phones to achieve high efficiency. The demands of portable electronics for low power consumption to extend battery life and reduce heat dissipation mandate efficient, high-performance audio amplifiers. The high efficiency of Class D amplifiers (CDAs) makes them particularly attractive for portable applications. The Digital class D amplifier is an interesting solution to increase the efficiency of embedded systems. However, this solution is not good enough in terms of PWM stage linearity and power supply rejection. An efficient control is needed to correct the error sources in order to get a high fidelity sound quality in the whole audio range of frequencies. A fundamental analysis on various error sources due to non idealities in the power stage have been discussed here with key focus on Power supply perturbations driving the Power stage of a Class D Audio Amplifier. Two types of closed loop Digital Class D architecture for PSRR improvement have been proposed and modeled. Double sided uniform sampling modulation has been used. One of the architecture uses feedback around the power stage and the second architecture uses feedback into digital domain. Simulation & experimental results confirm that the closed loop PSRR & PS-IMD improve by around 30-40 dB and 25 dB respectively.
ContributorsChakraborty, Bijeta (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2012
Description
Until late 1970’s the primary focus in power system modeling has been largely directed towards power system generation and transmission. Over the years, the importance of load modeling grew and having an accurate representation of load played an important role in the planning and operation studies. With an emphasis on tackling the topic of load modeling, this thesis presents the following intermediary steps in developing accurate load models:
1. Synthesis of a three-phase standard feeder and load model using the measured voltages and currents, for events such as faults and feeder pickup cases, obtained at the head of the feeder.
2. Investigated the impact of the synthesized standard feeder and load model on the sub-transmission system for a feeder pick-up case.
In the first phase of this project, a standard feeder and load model had been synthesized by capturing the current transients when three-phase voltage measurements (obtained from a local electric utility) are played-in as input to the synthesized model. The comparison between the measured currents and the simulated currents obtained using an electromagnetic transient analysis software (PSCAD) are made at the head of the designed feeder. The synthesized load model has a load composition which includes impedance loads, single-phase induction motor loads and three-phase induction motor loads. The parameters of the motor models are adjusted to obtain a good correspondence between measured three-phase currents and simulated current responses at the head of the feeder when subjected to events under which measurements were obtained on the feeder. These events include faults which occurred upstream of the feeder at a higher voltage level and a feeder pickup event that occurred downstream from the head of the feeder. Two different load compositions have been obtained for this feeder and load model depending on the types of load present in the surrounding area (residential or industrial/commercial).
The second phase of this project examines the impact of the feeder pick-up event on the 69 kV sub-transmission system using the obtained standard feeder and load model. Using the 69 kV network data obtained from a local utility, a sub-transmission network has been built in PSCAD. The main difference between the first and second phase of this project is that no measurements are played-in to the model in the latter case. Instead, the feeder pick-up event at a particular substation is simulated using the reduced equivalent of the 69 kV sub-transmission circuit together with the synthesized three-phase models of the feeder and the loads obtained in the first phase of the project. Using this analysis, it is observed that a good correspondence between the PSCAD simulated values of both three-phase voltages and currents with their corresponding measured responses at the substation is achieved.
1. Synthesis of a three-phase standard feeder and load model using the measured voltages and currents, for events such as faults and feeder pickup cases, obtained at the head of the feeder.
2. Investigated the impact of the synthesized standard feeder and load model on the sub-transmission system for a feeder pick-up case.
In the first phase of this project, a standard feeder and load model had been synthesized by capturing the current transients when three-phase voltage measurements (obtained from a local electric utility) are played-in as input to the synthesized model. The comparison between the measured currents and the simulated currents obtained using an electromagnetic transient analysis software (PSCAD) are made at the head of the designed feeder. The synthesized load model has a load composition which includes impedance loads, single-phase induction motor loads and three-phase induction motor loads. The parameters of the motor models are adjusted to obtain a good correspondence between measured three-phase currents and simulated current responses at the head of the feeder when subjected to events under which measurements were obtained on the feeder. These events include faults which occurred upstream of the feeder at a higher voltage level and a feeder pickup event that occurred downstream from the head of the feeder. Two different load compositions have been obtained for this feeder and load model depending on the types of load present in the surrounding area (residential or industrial/commercial).
The second phase of this project examines the impact of the feeder pick-up event on the 69 kV sub-transmission system using the obtained standard feeder and load model. Using the 69 kV network data obtained from a local utility, a sub-transmission network has been built in PSCAD. The main difference between the first and second phase of this project is that no measurements are played-in to the model in the latter case. Instead, the feeder pick-up event at a particular substation is simulated using the reduced equivalent of the 69 kV sub-transmission circuit together with the synthesized three-phase models of the feeder and the loads obtained in the first phase of the project. Using this analysis, it is observed that a good correspondence between the PSCAD simulated values of both three-phase voltages and currents with their corresponding measured responses at the substation is achieved.
ContributorsNekkalapu, Sameer (Author) / Vittal, Vijay (Thesis advisor) / Undrill, John M (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2018
Description
In this thesis, a digital input class D audio amplifier system which has the ability
to reject the power supply noise and nonlinearly of the output stage is presented. The main digital class D feed-forward path is using the fully-digital sigma-delta PWM open loop topology. Feedback loop is used to suppress the power supply noise and harmonic distortions. The design is using global foundry 0.18um technology.
Based on simulation, the power supply rejection at 200Hz is about -49dB with
81dB dynamic range and -70dB THD+N. The full scale output power can reach as high as 27mW and still keep minimum -68dB THD+N. The system efficiency at full scale is about 82%.
to reject the power supply noise and nonlinearly of the output stage is presented. The main digital class D feed-forward path is using the fully-digital sigma-delta PWM open loop topology. Feedback loop is used to suppress the power supply noise and harmonic distortions. The design is using global foundry 0.18um technology.
Based on simulation, the power supply rejection at 200Hz is about -49dB with
81dB dynamic range and -70dB THD+N. The full scale output power can reach as high as 27mW and still keep minimum -68dB THD+N. The system efficiency at full scale is about 82%.
ContributorsBai, Jing (Author) / Bakkaloglu, Bertan (Thesis advisor) / Arizona State University (Publisher)
Created2015
Description
Testing and calibration constitute a significant part of the overall manufacturing cost of microelectromechanical system (MEMS) devices. Developing a low-cost testing and calibration scheme applicable at the user side that ensures the continuous reliability and accuracy is a crucial need. The main purpose of testing is to eliminate defective devices and to verify the qualifications of a product is met. The calibration process for capacitive MEMS devices, for the most part, entails the determination of the mechanical sensitivity. In this work, a physical-stimulus-free built-in-self-test (BIST) integrated circuit (IC) design characterizing the sensitivity of capacitive MEMS accelerometers is presented. The BIST circuity can extract the amplitude and phase response of the acceleration sensor's mechanics under electrical excitation within 0.55% of error with respect to its mechanical sensitivity under the physical stimulus. Sensitivity characterization is performed using a low computation complexity multivariate linear regression model. The BIST circuitry maximizes the use of existing analog and mixed-signal readout signal chain and the host processor core, without the need for computationally expensive Fast Fourier Transform (FFT)-based approaches. The BIST IC is designed and fabricated using the 0.18-µm CMOS technology. The sensor analog front-end and BIST circuitry are integrated with a three-axis, low-g capacitive MEMS accelerometer in a single hermetically sealed package. The BIST circuitry occupies 0.3 mm2 with a total readout IC area of 1.0 mm2 and consumes 8.9 mW during self-test operation.
ContributorsOzel, Muhlis Kenan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2017
Description
Micro Electro Mechanical Systems (MEMS) based accelerometers are one of the most commonly used sensors out there. They are used in devices such as, airbags, smartphones, airplanes, and many more. Although they are very accurate, they degrade with time or get offset due to some damage. To fix this, they must be calibrated again using physical calibration technique, which is an expensive process to conduct. However, these sensors can also be calibrated infield by applying an on-chip electrical stimulus to the sensor. Electrical stimulus-based calibration could bring the cost of testing and calibration significantly down as compared to factory testing. In this thesis, simulations are presented to formulate a statistical prediction model based on an electrical stimulus. Results from two different approaches of electrical calibration have been discussed. A prediction model with a root mean square error of 1% has been presented in this work. Experiments were conducted on commercially available accelerometers to test the techniques used for simulations.
ContributorsBassi, Ishaan (Author) / Ozev, Sule (Thesis advisor) / Christen, Jennifer Blain (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2020