Matching Items (2)
Filtering by

Clear all filters

152415-Thumbnail Image.png
Description
We are expecting hundreds of cores per chip in the near future. However, scaling the memory architecture in manycore architectures becomes a major challenge. Cache coherence provides a single image of memory at any time in execution to all the cores, yet coherent cache architectures are believed will not scale

We are expecting hundreds of cores per chip in the near future. However, scaling the memory architecture in manycore architectures becomes a major challenge. Cache coherence provides a single image of memory at any time in execution to all the cores, yet coherent cache architectures are believed will not scale to hundreds and thousands of cores. In addition, caches and coherence logic already take 20-50% of the total power consumption of the processor and 30-60% of die area. Therefore, a more scalable architecture is needed for manycore architectures. Software Managed Manycore (SMM) architectures emerge as a solution. They have scalable memory design in which each core has direct access to only its local scratchpad memory, and any data transfers to/from other memories must be done explicitly in the application using Direct Memory Access (DMA) commands. Lack of automatic memory management in the hardware makes such architectures extremely power-efficient, but they also become difficult to program. If the code/data of the task mapped onto a core cannot fit in the local scratchpad memory, then DMA calls must be added to bring in the code/data before it is required, and it may need to be evicted after its use. However, doing this adds a lot of complexity to the programmer's job. Now programmers must worry about data management, on top of worrying about the functional correctness of the program - which is already quite complex. This dissertation presents a comprehensive compiler and runtime integration to automatically manage the code and data of each task in the limited local memory of the core. We firstly developed a Complete Circular Stack Management. It manages stack frames between the local memory and the main memory, and addresses the stack pointer problem as well. Though it works, we found we could further optimize the management for most cases. Thus a Smart Stack Data Management (SSDM) is provided. In this work, we formulate the stack data management problem and propose a greedy algorithm for the same. Later on, we propose a general cost estimation algorithm, based on which CMSM heuristic for code mapping problem is developed. Finally, heap data is dynamic in nature and therefore it is hard to manage it. We provide two schemes to manage unlimited amount of heap data in constant sized region in the local memory. In addition to those separate schemes for different kinds of data, we also provide a memory partition methodology.
ContributorsBai, Ke (Author) / Shrivastava, Aviral (Thesis advisor) / Chatha, Karamvir (Committee member) / Xue, Guoliang (Committee member) / Chakrabarti, Chaitali (Committee member) / Arizona State University (Publisher)
Created2014
133905-Thumbnail Image.png
Description
This thesis examines the impact of price changes of select microprocessors on the market share and 5-year gross profit net present values of Company X in the networking market through a multi-step analysis. The networking market includes segments including media processing, cloud services, security, routers & switches, and access points.

This thesis examines the impact of price changes of select microprocessors on the market share and 5-year gross profit net present values of Company X in the networking market through a multi-step analysis. The networking market includes segments including media processing, cloud services, security, routers & switches, and access points. For this thesis our team focused on the routers & switches, as well as the security segments. Company X wants to capitalize on the expected growth of the networking market as it transitions to its fifth generation (henceforth referred to as 5G) by positioning itself favorably in its customers eyes through high quality products offered at competitive prices. Our team performed a quantitative analysis of benchmark data to measure the performances of Company X's products against those of its competitors. We collected this data from third party computer reviewers, as well as the published reports of Company X and its competitors. Through the use of a preference matrix, we then normalized this performance data to adjust for different scales. In order to provide a well-rounded analysis, we adjusted these normalized performances for power consumption (using thermal design power as a proxy) as well as price. We believe these adjusted performances are more valuable than raw benchmark data, as they appeal to the demands of price-sensitive customers. Based on these comparisons, our team was able to assess price changes for their market and discounted financial impact on Company X. Our findings challenge the current pricing of one of the two products being analyzed and suggests a 9% decrease in the price of said product. This recommendation most effectively positions Company X for the development of 5G by offering the best balance of market share and NPV.
ContributorsArias, Stephen (Co-author) / Masson, Taylor (Co-author) / McCall, Kyle (Co-author) / Dimitroff, Alex (Co-author) / Hardy, Sebastian (Co-author) / Simonson, Mark (Thesis director) / Haller, Marcie (Committee member) / School of Accountancy (Contributor) / Department of Finance (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05