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Semiconductor device scaling has kept up with Moore's law for the past decades and they have been scaling by a factor of half every one and half years. Every new generation of device technology opens up new opportunities and challenges and especially so for analog design. High speed and low

Semiconductor device scaling has kept up with Moore's law for the past decades and they have been scaling by a factor of half every one and half years. Every new generation of device technology opens up new opportunities and challenges and especially so for analog design. High speed and low gain is characteristic of these processes and hence a tradeoff that can enable to get back gain by trading speed is crucial. This thesis proposes a solution that increases the speed of sampling of a circuit by a factor of three while reducing the specifications on analog blocks and keeping the power nearly constant. The techniques are based on the switched capacitor technique called Correlated Level Shifting. A triple channel Cyclic ADC has been implemented, with each channel working at a sampling frequency of 3.33MS/s and a resolution of 14 bits. The specifications are compared with that based on a traditional architecture to show the superiority of the proposed technique.
ContributorsSivakumar, Balasubramanian (Author) / Farahani, Bahar Jalali (Thesis advisor) / Garrity, Douglas (Committee member) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2012
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Two nested capacitors can produce work if the electric fields are not aligned, and the purpose of this research was to explore the possibility of using that generation instead of DC motors. The work the capacitors produce is determined by the strength of the fields and materials that is composed

Two nested capacitors can produce work if the electric fields are not aligned, and the purpose of this research was to explore the possibility of using that generation instead of DC motors. The work the capacitors produce is determined by the strength of the fields and materials that is composed of. The power density of the object is then determined by the volume. As the electric field increases in strength, the power increases, so to create a very strong internal field. The nested capacitors use a dielectric to prevent breakdown from the strength of the field. Additionally, as the nested capacitors decrease in size, their power density increases rapidly \u2014 becoming close to a dc motor's power density around the 500mm^2 size. When the result was simulated, it was discovered that the electric field was not contained to the dielectric and would result in sparking. Several other concerns would need to be addressed for this to become a viable solution.
ContributorsFryda, George Andrew (Author) / Singh, Anoop (Thesis director) / Yu, Hongbin (Committee member) / Mechanical and Aerospace Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
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Description
Silicon carbide (SiC) has always been considered as an excellent material for high temperature and high power devices. Since SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), it puts SiC in a unique position. Although SiC metal oxide semiconductor (MOS) technology has made significant progress

Silicon carbide (SiC) has always been considered as an excellent material for high temperature and high power devices. Since SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), it puts SiC in a unique position. Although SiC metal oxide semiconductor (MOS) technology has made significant progress in recent years, there are still a number of issues to be overcome before more commercial SiC devices can enter the market. The prevailing issues surrounding SiC MOSFET devices are the low channel mobility, the low quality of the oxide layer and the high interface state density at the SiC/SiO2 interface. Consequently, there is a need for research to be performed in order to have a better understanding of the factors causing the poor SiC/SiO2 interface properties. In this work, we investigated the generation lifetime in SiC materials by using the pulsed metal oxide semiconductor (MOS) capacitor method and measured the interface state density distribution at the SiC/SiO2 interface by using the conductance measurement and the high-low frequency capacitance technique. These measurement techniques have been performed on n-type and p-type SiC MOS capacitors. In the course of our investigation, we observed fast interface states at semiconductor-dielectric interfaces in SiC MOS capacitors that underwent three different interface passivation processes, such states were detected in the nitrided samples but not observed in PSG-passivated samples. This result indicate that the lack of fast states at PSG-passivated interface is one of the main reasons for higher channel mobility in PSG MOSFETs. In addition, the effect of mobile ions in the oxide on the response time of interface states has been investigated. In the last chapter we propose additional methods of investigation that can help elucidate the origin of the particular interface states, enabling a more complete understanding of the SiC/SiO2 material system.
ContributorsKao, Wei-Chieh (Author) / Goryll, Michael (Thesis advisor) / Chowdhury, Srabanti (Committee member) / Yu, Hongbin (Committee member) / Marinella, Matthew (Committee member) / Arizona State University (Publisher)
Created2015