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ContributorsShi, Ge (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-25
ContributorsShatuho, Kristina (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-27
ContributorsCarlisi, Daniel (Performer) / ASU Library. Music Library (Publisher)
Created2018-04-07
Description
Yannis Constantinidis was the last of the handful of composers referred to collectively as the Greek National School. The members of this group strove to create a distinctive national style for Greece, founded upon a synthesis of Western compositional idioms with melodic, rhyhmic, and modal features of their local folk traditions. Constantinidis particularly looked to the folk melodies of his native Asia Minor and the nearby Dodecanese Islands. His musical output includes operettas, musical comedies, orchestral works, chamber and vocal music, and much piano music, all of which draws upon folk repertories for thematic material. The present essay examines how he incorporates this thematic material in his piano compositions, written between 1943 and 1971, with a special focus on the 22 Songs and Dances from the Dodecanese. In general, Constantinidis's pianistic style is expressed through miniature pieces in which the folk tunes are presented mostly intact, but embedded in accompaniment based in early twentieth-century modal harmony. Following the dictates of the founding members of the Greek National School, Manolis Kalomiris and Georgios Lambelet, the modal basis of his harmonic vocabulary is firmly rooted in the characteristics of the most common modes of Greek folk music. A close study of his 22 Songs and Dances from the Dodecanese not only offers a valuable insight into his harmonic imagination, but also demonstrates how he subtly adapts his source melodies. This work also reveals his care in creating a musical expression of the words of the original folk songs, even in purely instrumental compositon.
ContributorsSavvidou, Dina (Author) / Hamilton, Robert (Thesis advisor) / Little, Bliss (Committee member) / Meir, Baruch (Committee member) / Thompson, Janice M (Committee member) / Arizona State University (Publisher)
Created2011
Description
This paper describes six representative works by twentieth-century Chinese composers: Jian-Zhong Wang, Er-Yao Lin, Yi-Qiang Sun, Pei-Xun Chen, Ying-Hai Li, and Yi Chen, which are recorded by the author on the CD. The six pieces selected for the CD all exemplify traits of Nationalism, with or without Western influences. Of the six works on the CD, two are transcriptions of the Han Chinese folk-like songs, one is a composition in the style of the Uyghur folk music, two are transcriptions of traditional Chinese instrumental music dating back to the eighteenth century, and one is an original composition in a contemporary style using folk materials. Two of the composers, who studied in the United States, were strongly influenced by Western compositional style. The other four, who did not study abroad, retained traditional Chinese style in their compositions. The pianistic level of difficulty in these six pieces varies from intermediate to advanced level. This paper includes biographical information for the six composers, background information on the compositions, and a brief analysis of each work. The author was exposed to these six pieces growing up, always believing that they are beautiful and deserve to be appreciated. When the author came to the United States for her studies, she realized that Chinese compositions, including these six pieces, were not sufficiently known to her peers. This recording and paper are offered in the hopes of promoting a wider familiarity with Chinese music and culture.
ContributorsLuo, Yali, D.M.A (Author) / Hamilton, Robert (Thesis advisor) / Campbell, Andrew (Committee member) / Pagano, Caio (Committee member) / Cosand, Walter (Committee member) / Rogers, Rodney (Committee member) / Arizona State University (Publisher)
Created2012
Description
The purpose of this project was to examine the lives and solo piano works of four members of the early generation of female composers in Taiwan. These four women were born between 1950 and 1960, began to appear on the Taiwanese musical scene after 1980, and were still active as composers at the time of this study. They include Fan-Ling Su (b. 1955), Hwei-Lee Chang (b. 1956), Shyh-Ji Pan-Chew (b. 1957), and Kwang-I Ying (b. 1960). Detailed biographical information on the four composers is presented and discussed. In addition, the musical form and features of all solo piano works at all levels by the four composers are analyzed, and the musical characteristics of each composer's work are discussed. The biography of a fifth composer, Wei-Ho Dai (b. 1950), is also discussed but is placed in the Appendices because her piano music could not be located. This research paper is presented in six chapters: (1) Prologue; the life and music of (2) Fan-Ling Su, (3) Hwei-Lee Chang, (4) Shyh-Ji Pan-Chew, and (5) Kwang-I Ying; and (6) Conclusion. The Prologue provides an overview of the development of Western classical music in Taiwan, a review of extant literature on the selected composers and their music, and the development of piano music in Taiwan. The Conclusion is comprised of comparisons of the four composers' music, including their personal interests and preferences as exhibited in their music. For example, all of the composers have used atonality in their music. Two of the composers, Fan-Ling Su and Kwang-I Ying, openly apply Chinese elements in their piano works, while Hwei-Lee Chang tries to avoid direct use of the Chinese pentatonic scale. The piano works of Hwei-Lee Chang and Shyh-Ji Pan-Chew are chromatic and atonal, and show an economical usage of material. Biographical information on Wei-Ho Dai and an overview of Taiwanese history are presented in the Appendices.
ContributorsWang, Jinding (Author) / Pagano, Caio (Thesis advisor) / Campbell, Andrew (Committee member) / Humphreys, Jere T. (Committee member) / Meyer-Thompson, Janice (Committee member) / Norton, Kay (Committee member) / Arizona State University (Publisher)
Created2011
ContributorsShi, Zhan (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-26
ContributorsLee, Eunhwa (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-17
ContributorsSuk, Mykola (Performer) / ASU Library. Music Library (Contributor)
Created2018-03-12
Description
Static CMOS logic has remained the dominant design style of digital systems for
more than four decades due to its robustness and near zero standby current. Static
CMOS logic circuits consist of a network of combinational logic cells and clocked sequential
elements, such as latches and flip-flops that are used for sequencing computations
over time. The majority of the digital design techniques to reduce power, area, and
leakage over the past four decades have focused almost entirely on optimizing the
combinational logic. This work explores alternate architectures for the flip-flops for
improving the overall circuit performance, power and area. It consists of three main
sections.
First, is the design of a multi-input configurable flip-flop structure with embedded
logic. A conventional D-type flip-flop may be viewed as realizing an identity function,
in which the output is simply the value of the input sampled at the clock edge. In
contrast, the proposed multi-input flip-flop, named PNAND, can be configured to
realize one of a family of Boolean functions called threshold functions. In essence,
the PNAND is a circuit implementation of the well-known binary perceptron. Unlike
other reconfigurable circuits, a PNAND can be configured by simply changing the
assignment of signals to its inputs. Using a standard cell library of such gates, a technology
mapping algorithm can be applied to transform a given netlist into one with
an optimal mixture of conventional logic gates and threshold gates. This approach
was used to fabricate a 32-bit Wallace Tree multiplier and a 32-bit booth multiplier
in 65nm LP technology. Simulation and chip measurements show more than 30%
improvement in dynamic power and more than 20% reduction in core area.
The functional yield of the PNAND reduces with geometry and voltage scaling.
The second part of this research investigates the use of two mechanisms to improve
the robustness of the PNAND circuit architecture. One is the use of forward and reverse body biases to change the device threshold and the other is the use of RRAM
devices for low voltage operation.
The third part of this research focused on the design of flip-flops with non-volatile
storage. Spin-transfer torque magnetic tunnel junctions (STT-MTJ) are integrated
with both conventional D-flipflop and the PNAND circuits to implement non-volatile
logic (NVL). These non-volatile storage enhanced flip-flops are able to save the state of
system locally when a power interruption occurs. However, manufacturing variations
in the STT-MTJs and in the CMOS transistors significantly reduce the yield, leading
to an overly pessimistic design and consequently, higher energy consumption. A
detailed analysis of the design trade-offs in the driver circuitry for performing backup
and restore, and a novel method to design the energy optimal driver for a given yield is
presented. Efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented,
in which the backup time is determined on a per-chip basis, resulting in minimizing
the energy wastage and satisfying the yield constraint. To achieve a yield of 98%,
the conventional approach would have to expend nearly 5X more energy than the
minimum required, whereas the proposed tunable approach expends only 26% more
energy than the minimum. A non-volatile threshold gate architecture NV-TLFF are
designed with the same backup and restore circuitry in 65nm technology. The embedded
logic in NV-TLFF compensates performance overhead of NVL. This leads to the
possibility of zero-overhead non-volatile datapath circuits. An 8-bit multiply-and-
accumulate (MAC) unit is designed to demonstrate the performance benefits of the
proposed architecture. Based on the results of HSPICE simulations, the MAC circuit
with the proposed NV-TLFF cells is shown to consume at least 20% less power and
area as compared to the circuit designed with conventional DFFs, without sacrificing
any performance.
more than four decades due to its robustness and near zero standby current. Static
CMOS logic circuits consist of a network of combinational logic cells and clocked sequential
elements, such as latches and flip-flops that are used for sequencing computations
over time. The majority of the digital design techniques to reduce power, area, and
leakage over the past four decades have focused almost entirely on optimizing the
combinational logic. This work explores alternate architectures for the flip-flops for
improving the overall circuit performance, power and area. It consists of three main
sections.
First, is the design of a multi-input configurable flip-flop structure with embedded
logic. A conventional D-type flip-flop may be viewed as realizing an identity function,
in which the output is simply the value of the input sampled at the clock edge. In
contrast, the proposed multi-input flip-flop, named PNAND, can be configured to
realize one of a family of Boolean functions called threshold functions. In essence,
the PNAND is a circuit implementation of the well-known binary perceptron. Unlike
other reconfigurable circuits, a PNAND can be configured by simply changing the
assignment of signals to its inputs. Using a standard cell library of such gates, a technology
mapping algorithm can be applied to transform a given netlist into one with
an optimal mixture of conventional logic gates and threshold gates. This approach
was used to fabricate a 32-bit Wallace Tree multiplier and a 32-bit booth multiplier
in 65nm LP technology. Simulation and chip measurements show more than 30%
improvement in dynamic power and more than 20% reduction in core area.
The functional yield of the PNAND reduces with geometry and voltage scaling.
The second part of this research investigates the use of two mechanisms to improve
the robustness of the PNAND circuit architecture. One is the use of forward and reverse body biases to change the device threshold and the other is the use of RRAM
devices for low voltage operation.
The third part of this research focused on the design of flip-flops with non-volatile
storage. Spin-transfer torque magnetic tunnel junctions (STT-MTJ) are integrated
with both conventional D-flipflop and the PNAND circuits to implement non-volatile
logic (NVL). These non-volatile storage enhanced flip-flops are able to save the state of
system locally when a power interruption occurs. However, manufacturing variations
in the STT-MTJs and in the CMOS transistors significantly reduce the yield, leading
to an overly pessimistic design and consequently, higher energy consumption. A
detailed analysis of the design trade-offs in the driver circuitry for performing backup
and restore, and a novel method to design the energy optimal driver for a given yield is
presented. Efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented,
in which the backup time is determined on a per-chip basis, resulting in minimizing
the energy wastage and satisfying the yield constraint. To achieve a yield of 98%,
the conventional approach would have to expend nearly 5X more energy than the
minimum required, whereas the proposed tunable approach expends only 26% more
energy than the minimum. A non-volatile threshold gate architecture NV-TLFF are
designed with the same backup and restore circuitry in 65nm technology. The embedded
logic in NV-TLFF compensates performance overhead of NVL. This leads to the
possibility of zero-overhead non-volatile datapath circuits. An 8-bit multiply-and-
accumulate (MAC) unit is designed to demonstrate the performance benefits of the
proposed architecture. Based on the results of HSPICE simulations, the MAC circuit
with the proposed NV-TLFF cells is shown to consume at least 20% less power and
area as compared to the circuit designed with conventional DFFs, without sacrificing
any performance.
ContributorsYang, Jinghua (Author) / Vrudhula, Sarma (Thesis advisor) / Barnaby, Hugh (Committee member) / Cao, Yu (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2018