Matching Items (5)
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- Creators: Kitchen, Jennifer
- Status: Published
Description
Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing.
This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor.
Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.
This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor.
Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.
ContributorsHegde, Ashwath (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2018
Description
Buck converters are a class of switched-mode power converters often used to step down DC input voltages to a lower DC output voltage. These converters naturally produce a current and voltage ripple at their output due to their switching action. Traditional methods of reducing this ripple have involved adding large discrete inductors and capacitors to filter the ripple, but large discrete components cannot be integrated onto chips. As an alternative to using passive filtering components, this project investigates the use of active ripple cancellation to reduce the peak output ripple. Hysteretic controlled buck converters were chosen for their simplicity of design and fast transient response. The proposed cancellation circuits sense the output ripple of the buck converter and inject an equal ripple exactly out of phase with the sensed ripple. Both current-mode and voltage-mode feedback loops are simulated, and the effectiveness of each cancellation circuit is examined. Results show that integrated active ripple cancellation circuits offer a promising substitute for large discrete filters.
ContributorsWang, Ziyan (Author) / Bakkaloglu, Bertan (Thesis director) / Kitchen, Jennifer (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2017-12
Description
In competitive Taekwondo, Electronic Body Protectors (EBPs) are used to register hits made by players during sparring. EBPs are comprised of three main components: chest guard, foot sock, and headgear. This equipment interacts with each other through the use of magnets, electric sensors, transmitters, and a receiver. The receiver is connected to a computer programmed with software to process signals from the transmitter and determine whether or not a competitor scored a point. The current design of EBPs, however, have numerous shortcomings, including sensing false positives, failing to register hits, costing too much, and relying on human judgment. This thesis will thoroughly delineate the operation of the current EBPs used and discuss research performed in order to eliminate these weaknesses.
ContributorsSpell, Valerie Anne (Author) / Kozicki, Michael (Thesis director) / Kitchen, Jennifer (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05
Description
This paper reviews several current designs of Cube Satellite (CubeSat) Electrical Power Systems (EPS) based on Silicon FET technologies and their current deficiencies, such as radiation-incurred defects and switching power losses. A strategy to fix these is proposed by the way of using Gallium Nitride (GaN) High Electron-Mobility Transistors (HEMTs) as switching devices within Buck/Boost Converters and other regulators. This work summarizes the EPS designs of several CubeSat missions, classifies them, and outlines their efficiency. An in-depth example of an EPS is also given, explaining the process in which these systems are designed. Areas of deficiency are explained along with reasoning as to why GaN can mitigate these losses, including its wide bandgap properties such as high RDS(on) and High Breakdown Voltage. Special design considerations must be kept in mind when using GaN HEMTs in this application and an example of a CubeSat using GaN HEMTs is mentioned. Finally, challenges ahead for GaN are explored including manufacturing considerations and long-term reliability.
ContributorsWilloughby, Alexander George (Author) / Kitchen, Jennifer (Thesis director) / Zhao, Yuji (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2017-05
Description
This thesis outlines the hand-held memory characterization testing system that is to be created into a PCB (printed circuit board). The circuit is designed to apply voltages diagonally through a RRAM cell (32x32 memory array). The purpose of this sweep across the RRAM is to measure and calculate the high and low resistance state value over a specified amount of testing cycles. With each cell having a unique output of high and low resistance states a unique characterization of each RRAM cell is able to be developed. Once the memory is characterized, the specific RRAM cell that was tested is then able to be used in a varying amount of applications for different things based on its uniqueness. Due to an inability to procure a packaged RRAM cell, a Mock-RRAM was instead designed in order to emulate the same behavior found in a RRAM cell.
The final testing circuit and Mock-RRAM are varied and complex but come together to be able to produce a measured value of the high resistance and low resistance state. This is done by the Arduino autonomously digitizing the anode voltage, cathode voltage, and output voltage. A ramp voltage that sweeps from 1V to -1V is applied to the Mock-RRAM acting as an input. This ramp voltage is then later defined as the anode voltage which is just one of the two nodes connected to the Mock-RRAM. The cathode voltage is defined as the other node at which the voltage drops across the Mock-RRAM. Using these three voltages as input to the Arduino, the Mock-RRAM path resistance is able to be calculated at any given point in time. Conducting many test cycles and calculating the high and low resistance values allows for a graph to be developed of the chaotic variation of resistance state values over time. This chaotic variation can then be analyzed further in the future in order to better predict trends and characterize the RRAM cell that was tested.
Furthermore, the interchangeability of many devices on the PCB allows for the testing system to do more in the future. Ports have been added to the final PCB in order to connect a packaged RRAM cell. This will allow for the characterization of a real RRAM memory cell later down the line rather than a Mock-RRAM as emulation. Due to the autonomous testing, very few human intervention is needed which makes this board a great baseline for others in the future looking to add to it and collect larger pools of data.
The final testing circuit and Mock-RRAM are varied and complex but come together to be able to produce a measured value of the high resistance and low resistance state. This is done by the Arduino autonomously digitizing the anode voltage, cathode voltage, and output voltage. A ramp voltage that sweeps from 1V to -1V is applied to the Mock-RRAM acting as an input. This ramp voltage is then later defined as the anode voltage which is just one of the two nodes connected to the Mock-RRAM. The cathode voltage is defined as the other node at which the voltage drops across the Mock-RRAM. Using these three voltages as input to the Arduino, the Mock-RRAM path resistance is able to be calculated at any given point in time. Conducting many test cycles and calculating the high and low resistance values allows for a graph to be developed of the chaotic variation of resistance state values over time. This chaotic variation can then be analyzed further in the future in order to better predict trends and characterize the RRAM cell that was tested.
Furthermore, the interchangeability of many devices on the PCB allows for the testing system to do more in the future. Ports have been added to the final PCB in order to connect a packaged RRAM cell. This will allow for the characterization of a real RRAM memory cell later down the line rather than a Mock-RRAM as emulation. Due to the autonomous testing, very few human intervention is needed which makes this board a great baseline for others in the future looking to add to it and collect larger pools of data.
ContributorsDobrin, Ryan Christopher (Co-author) / Halden, Matthew (Co-author) / Hall, Tanner (Co-author) / Barnaby, Hugh (Thesis director) / Kitchen, Jennifer (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2019-05