Matching Items (5)
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- All Subjects: ESL
- Creators: Lood, Adrienne
- Creators: Chatha, Karamvir S
- Member of: Theses and Dissertations
Description
In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.
ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Created2013
Description
Network-on-Chip (NoC) architectures have emerged as the solution to the on-chip communication challenges of multi-core embedded processor architectures. Design space exploration and performance evaluation of a NoC design requires fast simulation infrastructure. Simulation of register transfer level model of NoC is too slow for any meaningful design space exploration. One of the solutions to reduce the speed of simulation is to increase the level of abstraction. SystemC TLM2.0 provides the capability to model hardware design at higher levels of abstraction with trade-off of simulation speed and accuracy. In this thesis, SystemC TLM2.0 models of NoC routers are developed at three levels of abstraction namely loosely-timed, approximately-timed, and cycle accurate. Simulation speed and accuracy of these three models are evaluated by a case study of a 4x4 mesh NoC.
ContributorsArlagadda Narasimharaju, Jyothi Swaroop (Author) / Chatha, Karamvir S (Thesis advisor) / Sen, Arunabha (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2012
Description
The purpose of this research project was to assess the self-perceptions of academic and social success in bilingual college students, with a special comparison between students who did not speak English as their first language and students who did speak English as their first language. The bilingual participants were primarily recruited from Arizona State University (ASU) classes and international student organizations. In the survey, participants identified the languages they speak and provided ratings for the following: their English language proficiency, their preference and comfort level in various academic situations (e.g., visiting professors during office hours, studying for exams), their preference and comfort level in various social situations (e.g., making friends at college, language preference with friends), and their testing format preferences (e.g., multiple choice, essay). Participants also were asked to provide their opinions on tools that could be added to Canvas to assist students who do not speak English as their first language (e.g., translation dictionary). Results revealed that academic and social preferences were influenced by students’ level of English proficiency and reflect differences in confidence across settings. The summary findings will be utilized to create a list of recommendations for college faculty instructors and peer counselors to help mitigate the challenges faced by college bilingual students.
ContributorsLood, Adrienne (Author) / Azuma, Tamiko (Thesis director) / Rodriguez, Norma (Committee member) / Barrett, The Honors College (Contributor)
Created2023-05
ContributorsLood, Adrienne (Author) / Azuma, Tamiko (Thesis director) / Rodriguez, Norma (Committee member) / Barrett, The Honors College (Contributor)
Created2023-05
ContributorsLood, Adrienne (Author) / Azuma, Tamiko (Thesis director) / Rodriguez, Norma (Committee member) / Barrett, The Honors College (Contributor)
Created2023-05