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In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a

In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.
ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Network-on-Chip (NoC) architectures have emerged as the solution to the on-chip communication challenges of multi-core embedded processor architectures. Design space exploration and performance evaluation of a NoC design requires fast simulation infrastructure. Simulation of register transfer level model of NoC is too slow for any meaningful design space exploration. One

Network-on-Chip (NoC) architectures have emerged as the solution to the on-chip communication challenges of multi-core embedded processor architectures. Design space exploration and performance evaluation of a NoC design requires fast simulation infrastructure. Simulation of register transfer level model of NoC is too slow for any meaningful design space exploration. One of the solutions to reduce the speed of simulation is to increase the level of abstraction. SystemC TLM2.0 provides the capability to model hardware design at higher levels of abstraction with trade-off of simulation speed and accuracy. In this thesis, SystemC TLM2.0 models of NoC routers are developed at three levels of abstraction namely loosely-timed, approximately-timed, and cycle accurate. Simulation speed and accuracy of these three models are evaluated by a case study of a 4x4 mesh NoC.
ContributorsArlagadda Narasimharaju, Jyothi Swaroop (Author) / Chatha, Karamvir S (Thesis advisor) / Sen, Arunabha (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2012
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Description

The goal of this research is to increase understanding of the experience of foreign language anxiety (FLA) of Saudi Arabian students who are studying English as a Second Language (ESL) in the United States. Anxiety has been shown to significantly influence foreign language learning. Researchers have reported a negative correlation

The goal of this research is to increase understanding of the experience of foreign language anxiety (FLA) of Saudi Arabian students who are studying English as a Second Language (ESL) in the United States. Anxiety has been shown to significantly influence foreign language learning. Researchers have reported a negative correlation between academic achievement and anxiety. A growing body of research has provided greater insight into anxiety associated with learning foreign languages. In the 1980s, researchers began to focus on the connection between anxiety with foreign language learning, sometimes referred to as foreign language anxiety (FLA). Many studies aimed to identify the underlying factors associated with FLA. However, researchers studying FLA have argued a need for more research. Due to the significant number of Saudi students studying English in the United States at the time of this study, more research is needed to better understand these students’ experiences and the influences of FLA among this population. Therefore, the research question addressed in this study is: What are the factors that influence FLA among Saudi learners who are studying English in ESL classrooms in the United States? The study was conducted as a qualitative research design involving semi-structured interviews with 30 Saudi ESL students in the United States. My findings showed that these themes feeling unfamiliar with classroom activity, feeling unprepared for classroom activity, having unsuccessful attempts at communication, being judged negatively by others and having a negative perception of one’s own language reflect the general view of FLA as consisting of these three components (e.g., communication apprehension, test anxiety, and fear of negative evaluation). However, my findings also include some themes that do not fit neatly into the three-part model of FLA. The themes that emerged are: having a perception that English language is important, interacting with other sex from the same culture, encountering unfamiliar cultures, having teachers who behave in a negative way, and having teachers with negative characteristics. The findings of the current study suggests that the three component view of FLA might be insufficient for understanding FLA among Saudi Arabian ESL learners. So, I proposed three additional categories. The first category is teachers’ role that contains two themes: having teachers who behave in a negative way and having teachers with negative characteristics. The second category is cultural influence that contains two factors interacting with the opposite gender from the same culture and encountering unfamiliar culture. The third category is learners belief about language learning which has the factor having a perception that English language is important

ContributorsAlmotiary, Haifa (Author) / James, Mark MJ (Thesis advisor) / Matsuda, Aya AM (Committee member) / Van Geldern, Elly EVG (Committee member) / Arizona State University (Publisher)
Created2022