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- All Subjects: nanotechnology
Description
CMOS technology is expected to enter the 10nm regime for future integrated circuits (IC). Such aggressive scaling leads to vastly increased variability, posing a grand challenge to robust IC design. Variations in CMOS are often divided into two types: intrinsic variations and process-induced variations. Intrinsic variations are limited by fundamental physics. They are inherent to CMOS structure, considered as one of the ultimate barriers to the continual scaling of CMOS devices. In this work the three primary intrinsic variations sources are studied, including random dopant fluctuation (RDF), line-edge roughness (LER) and oxide thickness fluctuation (OTF). The research is focused on the modeling and simulation of those variations and their scaling trends. Besides the three variations, a time dependent variation source, Random Telegraph Noise (RTN) is also studied. Different from the other three variations, RTN does not contribute much to the total variation amount, but aggregate the worst case of Vth variations in CMOS. In this work a TCAD based simulation study on RTN is presented, and a new SPICE based simulation method for RTN is proposed for time domain circuit analysis. Process-induced variations arise from the imperfection in silicon fabrication, and vary from foundries to foundries. In this work the layout dependent Vth shift due to Rapid-Thermal Annealing (RTA) are investigated. In this work, we develop joint thermal/TCAD simulation and compact modeling tools to analyze performance variability under various layout pattern densities and RTA conditions. Moreover, we propose a suite of compact models that bridge the underlying RTA process with device parameter change for efficient design optimization.
ContributorsYe, Yun, Ph.D (Author) / Cao, Yu (Thesis advisor) / Yu, Hongbin (Committee member) / Song, Hongjiang (Committee member) / Clark, Lawrence (Committee member) / Arizona State University (Publisher)
Created2011
Description
Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and oxide thickness fluctuation. These variations greatly impact all aspects of circuit performance and pose a grand challenge to future robust IC design. To improve robustness, efficient methodology is required that considers effect of variations in the design flow. Analyzing timing variability of complex circuits with HSPICE simulations is very time consuming. This thesis proposes an analytical model to predict variability in CMOS circuits that is quick and accurate. There are several analytical models to estimate nominal delay performance but very little work has been done to accurately model delay variability. The proposed model is comprehensive and estimates nominal delay and variability as a function of transistor width, load capacitance and transition time. First, models are developed for library gates and the accuracy of the models is verified with HSPICE simulations for 45nm and 32nm technology nodes. The difference between predicted and simulated σ/μ for the library gates is less than 1%. Next, the accuracy of the model for nominal delay is verified for larger circuits including ISCAS'85 benchmark circuits. The model predicted results are within 4% error of HSPICE simulated results and take a small fraction of the time, for 45nm technology. Delay variability is analyzed for various paths and it is observed that non-critical paths can become critical because of Vth variation. Variability on shortest paths show that rate of hold violations increase enormously with increasing Vth variation.
ContributorsGummalla, Samatha (Author) / Chakrabarti, Chaitali (Thesis advisor) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
This dissertation proposes and presents two different passive sigma-delta
modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step
by step process designing the zoom-ADC along with a synthesis tool that can target various
design specifications are presented. The design flow does not rely on extensive knowledge
of an experienced ADC designer. Two example set of BIST ADCs have been synthesized
with different performance requirements in 65nm CMOS process. The first ADC achieves
90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW
power. Another example achieves 78.2dB SNR in 31.25µs measurement time and
consumes 63µW power. The second ADC architecture is a multi-mode, dynamically
zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating
flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the
fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)-
independent, dynamic zooming technique, employing an interpolating zooming front-end.
The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it
suitable for cellular applications including 4G radio systems. By reconfiguring the OSR,
bias current, and component parameters, optimal power consumption can be achieved for
every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an
SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW
power consumption from a 1.2 V supply.
modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step
by step process designing the zoom-ADC along with a synthesis tool that can target various
design specifications are presented. The design flow does not rely on extensive knowledge
of an experienced ADC designer. Two example set of BIST ADCs have been synthesized
with different performance requirements in 65nm CMOS process. The first ADC achieves
90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW
power. Another example achieves 78.2dB SNR in 31.25µs measurement time and
consumes 63µW power. The second ADC architecture is a multi-mode, dynamically
zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating
flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the
fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)-
independent, dynamic zooming technique, employing an interpolating zooming front-end.
The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it
suitable for cellular applications including 4G radio systems. By reconfiguring the OSR,
bias current, and component parameters, optimal power consumption can be achieved for
every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an
SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW
power consumption from a 1.2 V supply.
ContributorsEROL, OSMAN EMIR (Author) / Ozev, Sule (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ogras, Umit Y. (Committee member) / Blain-Christen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
To extend the lifetime of complementary metal-oxide-semiconductors (CMOS), emerging process techniques are being proposed to conquer the manufacturing difficulties. New structures and materials are proposed with superior electrical properties to traditional CMOS, such as strain technology and feedback field-effect transistor (FB-FET). To continue the design success and make an impact on leading products, advanced circuit design exploration must begin concurrently with early silicon development. Therefore, an accurate and scalable model is desired to correctly capture those effects and flexible to extend to alternative process choices. For example, strain technology has been successfully integrated into CMOS fabrication to improve transistor performance but the stress is non-uniformly distributed in the channel, leading to systematic performance variations. In this dissertation, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. On the other hand, semiconductor devices with self-feedback mechanisms are emerging as promising alternatives to CMOS. Fe-FET was proposed to improve the switching by integrating a ferroelectric material as gate insulator in a MOSFET structure. Under particular circumstances, ferroelectric capacitance is effectively negative, due to the negative slope of its polarization-electrical field curve. This property makes the ferroelectric layer a voltage amplifier to boost surface potential, achieving fast transition. A new threshold voltage model for Fe-FET is developed, and is further revealed that the impact of random dopant fluctuation (RDF) can be suppressed. Furthermore, through silicon via (TSV), a key technology that enables the 3D integration of chips, is studied. TSV structure is usually a cylindrical metal-oxide-semiconductors (MOS) capacitor. A piecewise capacitance model is proposed for 3D interconnect simulation. Due to the mismatch in coefficients of thermal expansion (CTE) among materials, thermal stress is observed in TSV process and impacts neighboring devices. The stress impact is investigated to support the interaction between silicon process and IC design at the early stage.
ContributorsWang, Chi-Chao (Author) / Cao, Yu (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Clark, Lawrence (Committee member) / Schroder, Dieter (Committee member) / Arizona State University (Publisher)
Created2011
Description
This work analyzes and develops a point-of-load (PoL) synchronous buck converter using enhancement-mode Gallium Nitride (e-GaN), with emphasis on optimizing reverse conduction loss by using a well-known technique of placing an anti-parallel Schottky diode across the synchronous power device. This work develops an improved analytical switching model for the GaN-based converter with the Schottky diode using piecewise linear approximations.
To avoid a shoot-through between the power switches of the buck converter, a small dead-time is inserted between gate drive switching transitions. Despite optimum dead-time management for a power converter, optimum dead-times vary for different load conditions. These variations become considerably large for PoL applications, which demand high output current with low output voltages. At high switching frequencies, these variations translate into losses that contribute significantly to the total loss of the converter. To understand and quantify power loss in a hard-switching buck converter that uses a GaN power device in parallel with a Schottky diode, piecewise transitions are used to develop an analytical switching model that quantifies the contribution of reverse conduction loss of GaN during dead-time.
The effects of parasitic elements on the dynamics of the switching converter are investigated during one switching cycle of the converter. A designed prototype of a buck converter is correlated to the predicted model to determine the accuracy of the model. This comparison is presented using simulations and measurements at 400 kHz and 2 MHz converter switching speeds for load (1A) condition and fixed dead-time values. Furthermore, performance of the buck converter with and without the Schottky diode is also measured and compared to demonstrate and quantify the enhanced performance when using an anti-parallel diode. The developed power converter achieves peak efficiencies of 91.7% and 93.86% for 2 MHz and 400 KHz switching frequencies, respectively, and drives load currents up to 6A for a voltage conversion from 12V input to 3.3V output.
In addition, various industry Schottky diodes have been categorized based on their packaging and electrical characteristics and the developed analytical model provides analytical expressions relating the diode characteristics to power stage performance parameters. The performance of these diodes has been characterized for different buck converter voltage step-down ratios that are typically used in industry applications and different switching frequencies ranging from 400 KHz to 2 MHz.
To avoid a shoot-through between the power switches of the buck converter, a small dead-time is inserted between gate drive switching transitions. Despite optimum dead-time management for a power converter, optimum dead-times vary for different load conditions. These variations become considerably large for PoL applications, which demand high output current with low output voltages. At high switching frequencies, these variations translate into losses that contribute significantly to the total loss of the converter. To understand and quantify power loss in a hard-switching buck converter that uses a GaN power device in parallel with a Schottky diode, piecewise transitions are used to develop an analytical switching model that quantifies the contribution of reverse conduction loss of GaN during dead-time.
The effects of parasitic elements on the dynamics of the switching converter are investigated during one switching cycle of the converter. A designed prototype of a buck converter is correlated to the predicted model to determine the accuracy of the model. This comparison is presented using simulations and measurements at 400 kHz and 2 MHz converter switching speeds for load (1A) condition and fixed dead-time values. Furthermore, performance of the buck converter with and without the Schottky diode is also measured and compared to demonstrate and quantify the enhanced performance when using an anti-parallel diode. The developed power converter achieves peak efficiencies of 91.7% and 93.86% for 2 MHz and 400 KHz switching frequencies, respectively, and drives load currents up to 6A for a voltage conversion from 12V input to 3.3V output.
In addition, various industry Schottky diodes have been categorized based on their packaging and electrical characteristics and the developed analytical model provides analytical expressions relating the diode characteristics to power stage performance parameters. The performance of these diodes has been characterized for different buck converter voltage step-down ratios that are typically used in industry applications and different switching frequencies ranging from 400 KHz to 2 MHz.
ContributorsKoli, Gauri (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2020