Matching Items (10)
Filtering by
- All Subjects: Materials Science
- Genre: Doctoral Dissertation
Description
This research emphasizes the use of low energy and low temperature post processing to improve the performance and lifetime of thin films and thin film transistors, by applying the fundamentals of interaction of materials with conductive heating and electromagnetic radiation. Single frequency microwave anneal is used to rapidly recrystallize the damage induced during ion implantation in Si substrates. Volumetric heating of the sample in the presence of the microwave field facilitates quick absorption of radiation to promote recrystallization at the amorphous-crystalline interface, apart from electrical activation of the dopants due to relocation to the substitutional sites. Structural and electrical characterization confirm recrystallization of heavily implanted Si within 40 seconds anneal time with minimum dopant diffusion compared to rapid thermal annealed samples. The use of microwave anneal to improve performance of multilayer thin film devices, e.g. thin film transistors (TFTs) requires extensive study of interaction of individual layers with electromagnetic radiation. This issue has been addressed by developing detail understanding of thin films and interfaces in TFTs by studying reliability and failure mechanisms upon extensive stress test. Electrical and ambient stresses such as illumination, thermal, and mechanical stresses are inflicted on the mixed oxide based thin film transistors, which are explored due to high mobilities of the mixed oxide (indium zinc oxide, indium gallium zinc oxide) channel layer material. Semiconductor parameter analyzer is employed to extract transfer characteristics, useful to derive mobility, subthreshold, and threshold voltage parameters of the transistors. Low temperature post processing anneals compatible with polymer substrates are performed in several ambients (oxygen, forming gas and vacuum) at 150 °C as a preliminary step. The analysis of the results pre and post low temperature anneals using device physics fundamentals assists in categorizing defects leading to failure/degradation as: oxygen vacancies, thermally activated defects within the bandgap, channel-dielectric interface defects, and acceptor-like or donor-like trap states. Microwave anneal has been confirmed to enhance the quality of thin films, however future work entails extending the use of electromagnetic radiation in controlled ambient to facilitate quick post fabrication anneal to improve the functionality and lifetime of these low temperature fabricated TFTs.
ContributorsVemuri, Rajitha (Author) / Alford, Terry L. (Thesis advisor) / Theodore, N David (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Inductors are fundamental components that do not scale well. Their physical limitations to scalability along with their inherent losses make them the main obstacle in achieving monolithic system-on-chip platform (SoCP). For past decades researchers focused on integrating magnetic materials into on-chip inductors in the quest of achieving high inductance density and quality factor (QF). The state of the art on-chip inductor is made of an enclosed magnetic thin-film around the current carrying wire for maximum flux amplification. Though the integration of magnetic materials results in enhanced inductor characteristics, this approach has its own challenges and limitations especially in power applications. The current-induced magnetic field (HDC) drives the magnetic film into its saturation state. At saturation, inductance and QF drop to that of air-core inductors, eliminating the benefits of integrating magnetic materials. Increasing the current carrying capability without substantially sacrificing benefits brought on by the magnetic material is an open challenge in power applications. Researchers continue to address this challenge along with the continuous improvement in inductance and QF for RF and power applications.
In this work on-chip inductors incorporating magnetic Co-4%Zr-4%Ta -8%B thin films were fabricated and their characteristics were examined under the influence of an externally applied DC magnetic field. It is well established that spins in magnetic materials tend to align themselves in the same direction as the applied field. The resistance of the inductor resulting from the ferromagnetic film can be changed by manipulating the orientation of magnetization. A reduction in resistance should lead to decreases in losses and an enhancement in the QF. The effect of externally applied DC magnetic field along the easy and hard axes was thoroughly investigated. Depending on the strength and orientation of the externally applied field significant improvements in QF response were gained at the expense of a relative reduction in inductance. Characteristics of magnetic-based inductors degrade with current-induced stress. It was found that applying an externally low DC magnetic field across the on-chip inductor prevents the degradation in inductance and QF responses. Examining the effect of DC magnetic field on current carrying capability under low temperature is suggested.
In this work on-chip inductors incorporating magnetic Co-4%Zr-4%Ta -8%B thin films were fabricated and their characteristics were examined under the influence of an externally applied DC magnetic field. It is well established that spins in magnetic materials tend to align themselves in the same direction as the applied field. The resistance of the inductor resulting from the ferromagnetic film can be changed by manipulating the orientation of magnetization. A reduction in resistance should lead to decreases in losses and an enhancement in the QF. The effect of externally applied DC magnetic field along the easy and hard axes was thoroughly investigated. Depending on the strength and orientation of the externally applied field significant improvements in QF response were gained at the expense of a relative reduction in inductance. Characteristics of magnetic-based inductors degrade with current-induced stress. It was found that applying an externally low DC magnetic field across the on-chip inductor prevents the degradation in inductance and QF responses. Examining the effect of DC magnetic field on current carrying capability under low temperature is suggested.
ContributorsKhdour, Mahmoud (Author) / Yu, Hongbin (Thesis advisor) / Pan, George (Committee member) / Goryll, Michael (Committee member) / Bearat, Hamdallah (Committee member) / Arizona State University (Publisher)
Created2014
Description
Semiconductor manufacturing economics necessitate the development of innovative device measurement techniques for quick assessment of products. Several novel electrical measurement techniques will be proposed for screening silicon device parameters. The studied parameters range from oxide reliability, and carrier lifetime in MOS capacitors to the power MOSFET reverse recovery.
It will be shown that positive charge trapping is a dominant process when thick oxides are stressed through the ramped voltage test (RVT). Exploiting the physics behind positive charge generation/trapping at high electric fields, a fast I-V measurement technique is proposed that can be used to effectively distinguish the ultra-thick oxides' intrinsic quality at low electric fields.
Next, two novel techniques will be presented for studying the carrier lifetime in MOS Capacitor devices. It will be shown that the deep-level transient spectroscopy (DLTS) can be applied to MOS test structures as a swift mean for screening the generation lifetime. Recombination lifetime will also be addressed by introducing the optically-excited MOS technique as a promising tool.
The last part of this work is devoted to the reverse recovery behavior of the body diode of power MOSFETs. The correct interpretation of the LDMOS reverse recovery is challenging and requires special attention. A simple approach will be presented to extract meaningful lifetime values from the reverse recovery of LDMOS body-diodes exploiting their gate voltage and the magnitude of the reverse bias.
It will be shown that positive charge trapping is a dominant process when thick oxides are stressed through the ramped voltage test (RVT). Exploiting the physics behind positive charge generation/trapping at high electric fields, a fast I-V measurement technique is proposed that can be used to effectively distinguish the ultra-thick oxides' intrinsic quality at low electric fields.
Next, two novel techniques will be presented for studying the carrier lifetime in MOS Capacitor devices. It will be shown that the deep-level transient spectroscopy (DLTS) can be applied to MOS test structures as a swift mean for screening the generation lifetime. Recombination lifetime will also be addressed by introducing the optically-excited MOS technique as a promising tool.
The last part of this work is devoted to the reverse recovery behavior of the body diode of power MOSFETs. The correct interpretation of the LDMOS reverse recovery is challenging and requires special attention. A simple approach will be presented to extract meaningful lifetime values from the reverse recovery of LDMOS body-diodes exploiting their gate voltage and the magnitude of the reverse bias.
ContributorsElhami Khorasani, Arash (Author) / Alford, Terry L. (Thesis advisor) / Goryll, Michael (Committee member) / Theodore, David (Committee member) / Arizona State University (Publisher)
Created2015
Description
Biogenic silica nanostructures, derived from diatoms, possess highly ordered porous hierarchical nanostructures and afford flexibility in design in large part due to the availability of a great variety of shapes, sizes, and symmetries. These advantages have been exploited for study of transport phenomena of ions and molecules towards the goal of developing ultrasensitive and selective filters and biosensors. Diatom frustules give researchers many inspiration and ideas for the design and production of novel nanostructured materials. In this doctoral research will focus on the following three aspects of biogenic silica: 1) Using diatom frustule as protein sensor. 2) Using diatom nanostructures as template to fabricate nano metal materials. 3) Using diatom nanostructures to fabricate hybrid platform.
Nanoscale confinement biogenetic silica template-based electrical biosensor assay offers the user the ability to detect and quantify the biomolecules. Diatoms have been demonstrated as part of a sensor. The sensor works on the principle of electrochemical impedance spectroscopy. When specific protein biomarkers from a test sample bind to corresponding antibodies conjugated to the surface of the gold surface at the base of each nanowell, a perturbation of electrical double layer occurs resulting in a change in the impedance.
Diatoms are also a new source of inspiration for the design and fabrication of nanostructured materials. Template-directed deposition within cylindrical nanopores of a porous membrane represents an attractive and reproducible approach for preparing metal nanopatterns or nanorods of a variety of aspect ratios. The nanopatterns fabricated from diatom have the potential of the metal-enhanced fluorescence to detect dye-conjugated molecules.
Another approach presents a platform integrating biogenic silica nanostructures with micromachined silicon substrates in a micro
ano hybrid device. In this study, one can take advantages of the unique properties of a marine diatom that exhibits nanopores on the order of 40 nm in diameter and a hierarchical structure. This device can be used to several applications, such as nano particles separation and detection. This platform is also a good substrate to study cell growth that one can observe the reaction of cell growing on the nanostructure of frustule.
Nanoscale confinement biogenetic silica template-based electrical biosensor assay offers the user the ability to detect and quantify the biomolecules. Diatoms have been demonstrated as part of a sensor. The sensor works on the principle of electrochemical impedance spectroscopy. When specific protein biomarkers from a test sample bind to corresponding antibodies conjugated to the surface of the gold surface at the base of each nanowell, a perturbation of electrical double layer occurs resulting in a change in the impedance.
Diatoms are also a new source of inspiration for the design and fabrication of nanostructured materials. Template-directed deposition within cylindrical nanopores of a porous membrane represents an attractive and reproducible approach for preparing metal nanopatterns or nanorods of a variety of aspect ratios. The nanopatterns fabricated from diatom have the potential of the metal-enhanced fluorescence to detect dye-conjugated molecules.
Another approach presents a platform integrating biogenic silica nanostructures with micromachined silicon substrates in a micro
ano hybrid device. In this study, one can take advantages of the unique properties of a marine diatom that exhibits nanopores on the order of 40 nm in diameter and a hierarchical structure. This device can be used to several applications, such as nano particles separation and detection. This platform is also a good substrate to study cell growth that one can observe the reaction of cell growing on the nanostructure of frustule.
ContributorsLin, Kai-Chun (Author) / Ramakrishna, B.L. (Thesis advisor) / Goryll, Michael (Thesis advisor) / Dey, Sandwip (Committee member) / Prasad, Shalini (Committee member) / Arizona State University (Publisher)
Created2014
Description
Photovoltaics (PV) is one of the promising options for maintaining sustainable energy supply because it is environmentally friendly, a non-polluting and low-maintenance energy source. Despite the many advantages of PV, solar energy currently accounts for only 1% of the global energy portfolio for electricity generation. This is because the cost of electricity from PV remains about a factor of two higher than the fossil fuel (10¢/kWh). Widely-used commercial methods employed to generate PV energy, such as silicon or thin film-based technologies, are still expensive as they are processed through vacuum-based techniques. Therefore, it is desirable to find an alternative method that is open-air and continuous process for the mass production of solar cells.
The objective of the research in this thesis is to develop low-cost spray pyrolysis technique to synthesize oxides thin films for applications in solar cells. Chapter 4 and 5 discuss spray-deposited dielectric oxides for their applications in Si solar cells. In Chapter 4, a successful deposition of Al2O3 is demonstrated using water as the solvent which ensures a lower cost and safer process environment. Optical, electrical, and structural properties of spray-deposited Al2O3 are investigated and compared to the industrial standard Atomic Layer Deposition (ALD) Al2O3/Plasma Enhanced Chemical Vapor Deposition (PECVD) SiNx stack, to reveal the suitability of spray-deposited Al2O3 for rear passivation and optical trapping in p-type Si Passivated Emitter and Rear Cell (PERC) solar cells. In Chapter 5, The possibility of using low-cost spray-deposited ZrO2 as the antireflection coating for Si solar cells is investigated. Optical, electrical and structural properties of spray-deposited ZrO2 films are studied and compared to the industrial standard antireflection coating PECVD SiNx. In Chapter 6, spray-deposited hematite Fe2O3 and sol-gel prepared anatase TiO2 thin films are sulfurized by annealing in H2S to investigate the band gap narrowing by sulfur doping and explore the possibility of using ternary semiconductors for their application as solar absorbers.
The objective of the research in this thesis is to develop low-cost spray pyrolysis technique to synthesize oxides thin films for applications in solar cells. Chapter 4 and 5 discuss spray-deposited dielectric oxides for their applications in Si solar cells. In Chapter 4, a successful deposition of Al2O3 is demonstrated using water as the solvent which ensures a lower cost and safer process environment. Optical, electrical, and structural properties of spray-deposited Al2O3 are investigated and compared to the industrial standard Atomic Layer Deposition (ALD) Al2O3/Plasma Enhanced Chemical Vapor Deposition (PECVD) SiNx stack, to reveal the suitability of spray-deposited Al2O3 for rear passivation and optical trapping in p-type Si Passivated Emitter and Rear Cell (PERC) solar cells. In Chapter 5, The possibility of using low-cost spray-deposited ZrO2 as the antireflection coating for Si solar cells is investigated. Optical, electrical and structural properties of spray-deposited ZrO2 films are studied and compared to the industrial standard antireflection coating PECVD SiNx. In Chapter 6, spray-deposited hematite Fe2O3 and sol-gel prepared anatase TiO2 thin films are sulfurized by annealing in H2S to investigate the band gap narrowing by sulfur doping and explore the possibility of using ternary semiconductors for their application as solar absorbers.
ContributorsShin, Woo Jung (Author) / Tao, Meng (Thesis advisor) / Goryll, Michael (Committee member) / Wang, Qing Hua (Committee member) / Arizona State University (Publisher)
Created2019
Description
InAs/InAsSb type-II superlattices (T2SLs) can be considered as potential alternatives for conventional HgCdTe photodetectors due to improved uniformity, lower manufacturing costs with larger substrates, and possibly better device performance. This dissertation presents a comprehensive study on the structural, optical and electrical properties of InAs/InAsSb T2SLs grown by Molecular Beam Epitaxy.
The effects of different growth conditions on the structural quality were thoroughly investigated. Lattice-matched condition was successfully achieved and material of exceptional quality was demonstrated.
After growth optimization had been achieved, structural defects could hardly be detected, so different characterization techniques, including etch-pit-density (EPD) measurements, cathodoluminescence (CL) imaging and X-ray topography (XRT), were explored, in attempting to gain better knowledge of the sparsely distributed defects. EPD revealed the distribution of dislocation-associated pits across the wafer. Unfortunately, the lack of contrast in images obtained by CL imaging and XRT indicated their inability to provide any quantitative information about defect density in these InAs/InAsSb T2SLs.
The nBn photodetectors based on mid-wave infrared (MWIR) and long-wave infrared (LWIR) InAs/InAsSb T2SLs were fabricated. The significant difference in Ga composition in the barrier layer coupled with different dark current behavior, suggested the possibility of different types of band alignment between the barrier layers and the absorbers. A positive charge density of 1.8 × 1017/cm3 in the barrier of MWIR nBn photodetector, as determined by electron holography, confirmed the presence of a potential well in its valence band, thus identifying type-II alignment. In contrast, the LWIR nBn photodetector was shown to have type-I alignment because no sign of positive charge was detected in its barrier.
Capacitance-voltage measurements were performed to investigate the temperature dependence of carrier densities in a metal-oxide-semiconductor (MOS) structure based on MWIR InAs/InAsSb T2SLs, and a nBn structure based on LWIR InAs/InAsSb T2SLs. No carrier freeze-out was observed in either sample, indicating very shallow donor levels. The decrease in carrier density when temperature increased was attributed to the increased density of holes that had been thermally excited from localized states near the oxide/semiconductor interface in the MOS sample. No deep-level traps were revealed in deep-level transient spectroscopy temperature scans.
The effects of different growth conditions on the structural quality were thoroughly investigated. Lattice-matched condition was successfully achieved and material of exceptional quality was demonstrated.
After growth optimization had been achieved, structural defects could hardly be detected, so different characterization techniques, including etch-pit-density (EPD) measurements, cathodoluminescence (CL) imaging and X-ray topography (XRT), were explored, in attempting to gain better knowledge of the sparsely distributed defects. EPD revealed the distribution of dislocation-associated pits across the wafer. Unfortunately, the lack of contrast in images obtained by CL imaging and XRT indicated their inability to provide any quantitative information about defect density in these InAs/InAsSb T2SLs.
The nBn photodetectors based on mid-wave infrared (MWIR) and long-wave infrared (LWIR) InAs/InAsSb T2SLs were fabricated. The significant difference in Ga composition in the barrier layer coupled with different dark current behavior, suggested the possibility of different types of band alignment between the barrier layers and the absorbers. A positive charge density of 1.8 × 1017/cm3 in the barrier of MWIR nBn photodetector, as determined by electron holography, confirmed the presence of a potential well in its valence band, thus identifying type-II alignment. In contrast, the LWIR nBn photodetector was shown to have type-I alignment because no sign of positive charge was detected in its barrier.
Capacitance-voltage measurements were performed to investigate the temperature dependence of carrier densities in a metal-oxide-semiconductor (MOS) structure based on MWIR InAs/InAsSb T2SLs, and a nBn structure based on LWIR InAs/InAsSb T2SLs. No carrier freeze-out was observed in either sample, indicating very shallow donor levels. The decrease in carrier density when temperature increased was attributed to the increased density of holes that had been thermally excited from localized states near the oxide/semiconductor interface in the MOS sample. No deep-level traps were revealed in deep-level transient spectroscopy temperature scans.
ContributorsShen, Xiaomeng (Author) / Zhang, Yong-Hang (Thesis advisor) / Smith, David J. (Thesis advisor) / Alford, Terry (Committee member) / Goryll, Michael (Committee member) / Mccartney, Martha R (Committee member) / Arizona State University (Publisher)
Created2015
Description
This work demonstrates novel nBn photodetectors including mid-wave infrared (MWIR) nBn photodetectors based on InAs/InAsSb type-II superlattices (T2SLs) with charge as the output signal, and visible nBn photodetectors based on CdTe with current output. Furthermore, visible/MWIR two-color photodetectors (2CPDs) are fabricated through monolithic integration of the CdTe nBn photodetector and an InSb photodiode.
The MWIR nBn photodetectors have a potential well for holes present in the barrier layer. At low voltages of < −0.2 V, which ensure low dark current <10-5 A/cm2 at 77 K, photogenerated holes are collected in this well with a storage lifetime of 40 s. This charge collection process is an in-device signal integration process that reduces the random noise significantly. Since the stored holes can be readout laterally as in charge-coupled devices, it is therefore possible to make charge-output nBn with much lower noise than conventional current-output nBn photodetectors.
The visible nBn photodetectors have a CdTe absorber layer and a ZnTe barrier layer with an aligned valence band edge. By using a novel ITO/undoped-CdTe top contact design, it has achieved a high specific detectivity of 3×1013 cm-Hz1/2/W at room temperature. Particularly, this CdTe nBn photodetector grown on InSb substrates enables the monolithic integration of CdTe and InSb photodetectors, and provides a platform to study in-depth device physics of nBn photodetectors at room temperature.
Furthermore, the visible/MWIR 2CPD has been developed by the monolithic integration of the CdTe nBn and an InSb photodiode through an n-CdTe/p-InSb tunnel junction. At 77 K, the photoresponse of the 2CPD can be switched between a 1-5.5 μm MWIR band and a 350-780 nm visible band by illuminating the device with an external light source or not, and applying with proper voltages. Under optimum conditions, the 2CPD has achieved a MWIR peak responsivity of 0.75 A/W with a band rejection ratio (BRR) of 52 dB, and a visible peak responsivity of 0.3 A/W with a BRR of 18 dB. This 2CPD has enabled future compact image sensors with high fill-factor and responsivity switchable between visible and MWIR colors.
The MWIR nBn photodetectors have a potential well for holes present in the barrier layer. At low voltages of < −0.2 V, which ensure low dark current <10-5 A/cm2 at 77 K, photogenerated holes are collected in this well with a storage lifetime of 40 s. This charge collection process is an in-device signal integration process that reduces the random noise significantly. Since the stored holes can be readout laterally as in charge-coupled devices, it is therefore possible to make charge-output nBn with much lower noise than conventional current-output nBn photodetectors.
The visible nBn photodetectors have a CdTe absorber layer and a ZnTe barrier layer with an aligned valence band edge. By using a novel ITO/undoped-CdTe top contact design, it has achieved a high specific detectivity of 3×1013 cm-Hz1/2/W at room temperature. Particularly, this CdTe nBn photodetector grown on InSb substrates enables the monolithic integration of CdTe and InSb photodetectors, and provides a platform to study in-depth device physics of nBn photodetectors at room temperature.
Furthermore, the visible/MWIR 2CPD has been developed by the monolithic integration of the CdTe nBn and an InSb photodiode through an n-CdTe/p-InSb tunnel junction. At 77 K, the photoresponse of the 2CPD can be switched between a 1-5.5 μm MWIR band and a 350-780 nm visible band by illuminating the device with an external light source or not, and applying with proper voltages. Under optimum conditions, the 2CPD has achieved a MWIR peak responsivity of 0.75 A/W with a band rejection ratio (BRR) of 52 dB, and a visible peak responsivity of 0.3 A/W with a BRR of 18 dB. This 2CPD has enabled future compact image sensors with high fill-factor and responsivity switchable between visible and MWIR colors.
ContributorsHe, Zhaoyu (Author) / Zhang, Yong-Hang (Thesis advisor) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Johnson, Shane (Committee member) / Arizona State University (Publisher)
Created2016
Description
The silicon-based solar cell has been extensively deployed in photovoltaic industry and plays an important role in renewable energy industries. A more energy-efficient, environment-harmless and eco-friendly silicon production technique is required for price-competitive solar energy harvesting. Silicon electrorefining in molten salt is promising for the ultrapure solar-grade Si production. To avoid using highly corrosive fluoride salt, CaCl2-based salt is widely employed for silicon electroreduction. For Si electroreduction in CaCl2-based salt, CaO is usually added to enhance the solubility of SiO2. However, the existence of oxygen in molten salt could result in system corrosion, anode passivation and the co-deposition of secondary phases such as CaSiO3 and SiO2 at the cathode. This research focuses on the development of reusable oxygen-free CaCl2-based molten salt for solar-grade silicon electrorefining. A new multi-potential electropurification process has been proposed and proven to be more effective in impurities removal. The as-received salt and the salt after electrorefining have been electropurified. The inductively-coupled plasma mass spectrometry and cyclic voltammetry have been utilized to determine the impurities removal of electropurification. The salt after silicon electrorefining has been regenerated to its original purity level before by the multi-potential electropurification process, demonstrating the feasibility of a reusable salt by electropurification. In an oxygen-free CaCl2-based salt without silicon precursor, the silicon dissolved from the silicon anode can be successfully deposited at the cathode. The silicon anode has been operated for more than 50 hours without passivation in the oxygen-free system. Silicon ions start to be deposited after 0.17 g of silicon has been dissolved into the salt from the silicon anode. A 180 µm deposit with a silver-luster surface was obtained at the cathode. The main impurities in the silicon anode such as aluminum, iron and titanium were not found in the silicon deposits. No oxygen-containing secondary phases are detected in the silicon deposits. These results confirm the feasibility of silicon electrorefining in the oxygen-free CaCl2-based salt.
ContributorsTseng, Mao-Feng (Author) / Tao, Meng (Thesis advisor) / Kannan, Arunachala Mada (Committee member) / Mu, Linqin (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2023
Description
Programmable Metallization Cell (PMC) devices are, in essence, redox-based
solid-state resistive switching devices that rely on ion transport through a solid electrolyte (SE) layer from anode to cathode. Analysis and modeling of the effect of different fabrication and processing parameter/conditions on PMC devices are crucial for future electronics. Furthermore, this work is even more significant for devices utilizing back-end- of-line (BEOL) compatible materials such as Cu, W, their oxides and SiOx as these devices offer cost effectiveness thanks to their inherent foundry-ready nature. In this dissertation, effect of annealing conditions and cathode material on the performance of Cu-SiOx vertical devices is investigated which shows that W-based devices have much lower forming voltage and initial resistance values. Also, higher annealing temperatures first lead to an increase in forming voltage from 400 °C to 500 °C, then a drastic decrease at 550 °C due to Cu island formation at the Cu/SiOx interface. Next, the characterization and modeling of the bilayer Cu2O/Cu-WO3 obtained by annealing the deposited Cu/WO3 stacks in air at BEOL-compatible temperatures is presented that display unique characteristics for lateral PMC devices. First, thin film oxidation kinetics of Cu is studied which show a parabolic relationship with annealing time and an activation energy of 0.70 eV. Grown Cu2O shows a cauliflower-like morphology where feature size on the surface increase with annealing time and temperature. Then, diffusion kinetics of Cu in WO3 is examined where the activation energy of diffusion of Cu into WO3 is calculated to be 0.74 eV. Cu was found to form clusters in the WO3 host which was revealed by imaging. Moreover, using the oxidation and diffusion analyses, a Matlab model is established for modeling the bilayer for process and annealing-condition optimization. The model is built to produce the resulting Cu2O thickness and Cu concentration in Cu-WO3. Additionally, material characterization, preliminary electrical results along with modeling of lateral PMC devices utilizing the bilayer is also demonstrated. By tuning the process parameters such as deposited Cu thickness and annealing conditions, a low-resistive Cu2O layer was achieved which dramatically enhanced the electrodeposition growth rate for lateral PMC devices.
solid-state resistive switching devices that rely on ion transport through a solid electrolyte (SE) layer from anode to cathode. Analysis and modeling of the effect of different fabrication and processing parameter/conditions on PMC devices are crucial for future electronics. Furthermore, this work is even more significant for devices utilizing back-end- of-line (BEOL) compatible materials such as Cu, W, their oxides and SiOx as these devices offer cost effectiveness thanks to their inherent foundry-ready nature. In this dissertation, effect of annealing conditions and cathode material on the performance of Cu-SiOx vertical devices is investigated which shows that W-based devices have much lower forming voltage and initial resistance values. Also, higher annealing temperatures first lead to an increase in forming voltage from 400 °C to 500 °C, then a drastic decrease at 550 °C due to Cu island formation at the Cu/SiOx interface. Next, the characterization and modeling of the bilayer Cu2O/Cu-WO3 obtained by annealing the deposited Cu/WO3 stacks in air at BEOL-compatible temperatures is presented that display unique characteristics for lateral PMC devices. First, thin film oxidation kinetics of Cu is studied which show a parabolic relationship with annealing time and an activation energy of 0.70 eV. Grown Cu2O shows a cauliflower-like morphology where feature size on the surface increase with annealing time and temperature. Then, diffusion kinetics of Cu in WO3 is examined where the activation energy of diffusion of Cu into WO3 is calculated to be 0.74 eV. Cu was found to form clusters in the WO3 host which was revealed by imaging. Moreover, using the oxidation and diffusion analyses, a Matlab model is established for modeling the bilayer for process and annealing-condition optimization. The model is built to produce the resulting Cu2O thickness and Cu concentration in Cu-WO3. Additionally, material characterization, preliminary electrical results along with modeling of lateral PMC devices utilizing the bilayer is also demonstrated. By tuning the process parameters such as deposited Cu thickness and annealing conditions, a low-resistive Cu2O layer was achieved which dramatically enhanced the electrodeposition growth rate for lateral PMC devices.
ContributorsBalaban, Mehmet Bugra (Author) / Kozicki, Michael N (Thesis advisor) / Barnaby, Hugh J (Committee member) / Goryll, Michael (Committee member, Committee member) / Arizona State University (Publisher)
Created2020
Description
Crystalline silicon covers more than 85% of the global photovoltaics industry and has sustained a nearly 30% year-over-year growth rate. Continued cost and capital expenditure (CAPEX) reductions are needed to sustain this growth. Using thin silicon wafers well below the current industry standard of 160 µm can reduce manufacturing cost, CAPEX, and levelized cost of electricity. Additionally, thinner wafers enable more flexible and lighter module designs, making them more compelling in market segments like building-integrated photovoltaics, portable power, aerospace, and automotive industries. Advanced architectures and superior surface passivation schemes are needed to enable the use of very thin silicon wafers. Silicon heterojunction (SHJ) and SHJ with interdigitated back contact solar cells have demonstrated open-circuit voltages surpassing 720 mV and the potential to surpass 25% conversion efficiency. These factors have led to an increasing interest in exploring SHJ solar cells on thin wafers. In this work, the passivation capability of the thin intrinsic hydrogenated amorphous silicon layer is improved by controlling the deposition temperature and the silane-to-hydrogen dilution ratio. An effective way to parametrize surface recombination is by using surface saturation current density and a very low surface saturation density is achieved on textured wafers for wafer thicknesses ranging between 40 and 180 µm which is an order of magnitude lesser compared to the prevalent industry standards. Implied open-circuit voltages over 760 mV were accomplished on SHJ structures deposited on n-type silicon wafers with thicknesses below 50 µm. An analytical model is also described for a better understanding of the variation of the recombination fractions for varying substrate thicknesses. The potential of using very thin wafers is also established by manufacturing SHJ solar cells, using industrially pertinent processing steps, on 40 µm thin standalone wafers while achieving maximum efficiency of 20.7%. It is also demonstrated that 40 µm thin SHJ solar cells can be manufactured using these processes on large areas. An analysis of the percentage contribution of current, voltage, and resistive losses are also characterized for the SHJ devices fabricated in this work for varying substrate thicknesses.
ContributorsBalaji, Pradeep (Author) / Bowden, Stuart (Thesis advisor) / Alford, Terry (Thesis advisor) / Goryll, Michael (Committee member) / Augusto, Andre (Committee member) / Arizona State University (Publisher)
Created2021