Matching Items (78)
Filtering by

Clear all filters

151474-Thumbnail Image.png
Description
The medical industry has benefited greatly by electronic integration resulting in the explosive growth of active medical implants. These devices often treat and monitor chronic health conditions and require very minimal power usage. A key part of these medical implants is an ultra-low power two way wireless communication system. This

The medical industry has benefited greatly by electronic integration resulting in the explosive growth of active medical implants. These devices often treat and monitor chronic health conditions and require very minimal power usage. A key part of these medical implants is an ultra-low power two way wireless communication system. This enables both control of the implant as well as relay of information collected. This research has focused on a high performance receiver for medical implant applications. One commonly quoted specification to compare receivers is energy per bit required. This metric is useful, but incomplete in that it ignores Sensitivity level, bit error rate, and immunity to interferers. In this study exploration of receiver architectures and convergence upon a comprehensive solution is done. This analysis is used to design and build a system for validation. The Direct Conversion Receiver architecture implemented for the MICS standard in 0.18 µm CMOS process consumes approximately 2 mW is competitive with published research.
ContributorsStevens, Mark (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
151252-Thumbnail Image.png
Description
Semiconductor device scaling has kept up with Moore's law for the past decades and they have been scaling by a factor of half every one and half years. Every new generation of device technology opens up new opportunities and challenges and especially so for analog design. High speed and low

Semiconductor device scaling has kept up with Moore's law for the past decades and they have been scaling by a factor of half every one and half years. Every new generation of device technology opens up new opportunities and challenges and especially so for analog design. High speed and low gain is characteristic of these processes and hence a tradeoff that can enable to get back gain by trading speed is crucial. This thesis proposes a solution that increases the speed of sampling of a circuit by a factor of three while reducing the specifications on analog blocks and keeping the power nearly constant. The techniques are based on the switched capacitor technique called Correlated Level Shifting. A triple channel Cyclic ADC has been implemented, with each channel working at a sampling frequency of 3.33MS/s and a resolution of 14 bits. The specifications are compared with that based on a traditional architecture to show the superiority of the proposed technique.
ContributorsSivakumar, Balasubramanian (Author) / Farahani, Bahar Jalali (Thesis advisor) / Garrity, Douglas (Committee member) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2012
149402-Thumbnail Image.png
Description
A dual-channel directional digital hearing aid (DHA) front end using Micro Electro Mechanical System (MEMS) microphones and an adaptive-power analog processing signal chain is presented. The analog front end consists of a double differential amplifier (DDA) based capacitance to voltage conversion circuit, 40dB variable gain amplifier (VGA) and a continuous

A dual-channel directional digital hearing aid (DHA) front end using Micro Electro Mechanical System (MEMS) microphones and an adaptive-power analog processing signal chain is presented. The analog front end consists of a double differential amplifier (DDA) based capacitance to voltage conversion circuit, 40dB variable gain amplifier (VGA) and a continuous time sigma delta analog to digital converter (CT - ΣΔ ADC). Adaptive power scaling of the 4th order CT - ΣΔ achieves 68dB SNR at 120μW, which can be scaled down to 61dB SNR at 67μW. This power saving will increse the battery life of the DHA.
ContributorsDeligoz, Ilker (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Jalali-Farahani, Bahar (Committee member) / Aberle, James T., 1961- (Committee member) / Chae, Junseok (Committee member) / Arizona State University (Publisher)
Created2010
ContributorsMoio, Dom (Director) / Latin Jazz Ensemble (Performer) / ASU Library. Music Library (Publisher)
Created2003-04-21
ContributorsMoio, Dom (Director) / Latin Jazz Ensemble (Performer) / ASU Library. Music Library (Publisher)
Created2004-11-15
ContributorsPilafian, Sam (Performer) / Malaby, Tony (Performer) / DiBartolo, Joel (Performer) / Moio, Dom (Performer) / Joel DiBartolo Tentet (Performer) / ASU Library. Music Library (Publisher)
Created1995-03-08
ContributorsClayton, John (Performer) / DiBartolo, Joel (Performer) / Clayton, Gerald (Performer) / Kocour, Mike (Performer) / Moio, Dom (Performer) / ASU Library. Music Library (Publisher)
Created2009-03-07
ContributorsPilafian, Sam (Performer) / Marohnic, Chuck (Performer) / Lovelady, Hugh (Performer) / Ruth, Bryon (Performer) / Jones, Warren (Performer) / Moio, Dom (Performer) / Young Sounds of Arizona (Performer) / Arizona Jazz Faculty Nonet (Performer) / ASU Library. Music Library (Publisher)
Created1999-03-08
ContributorsKocour, Mike (Performer) / Rotaru, Catalin (Performer) / Moio, Dom (Performer) / ASU Library. Music Library (Publisher)
Created2007-10-11
ContributorsMoio, Dom (Director) / Latin Jazz Band (Performer) / ASU Library. Music Library (Publisher)
Created2007-10-22