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- Genre: Masters Thesis
Description
As residential photovoltaic (PV) systems become more and more common and widespread, their system architectures are being developed to maximize power extraction while keeping the cost of associated electronics to a minimum. An architecture that has become popular in recent years is the "DC optimizer" architecture, wherein one DC-DC converter is connected to the output of each PV module. The DC optimizer architecture has the advantage of performing maximum power-point tracking (MPPT) at the module level, without the high cost of using an inverter on each module (the "microinverter" architecture). This work details the design of a proposed DC optimizer. The design incorporates a series-input parallel-output topology to implement MPPT at the sub-module level. This topology has some advantages over the more common series-output DC optimizer, including relaxed requirements for the system's inverter. An autonomous control scheme is proposed for the series-connected converters, so that no external control signals are needed for the system to operate, other than sunlight. The DC optimizer in this work is designed with an emphasis on efficiency, and to that end it uses GaN FETs and an active clamp technique to reduce switching and conduction losses. As with any parallel-output converter, phase interleaving is essential to minimize output RMS current losses. This work proposes a novel phase-locked loop (PLL) technique to achieve interleaving among the series-input converters.
ContributorsLuster, Daniel (Author) / Ayyanar, Raja (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2014
Description
Gallium Nitride (GaN) based Current Aperture Vertical Electron Transistors (CAVETs) present many appealing qualities for applications in high power, high frequency devices. The wide bandgap, high carrier velocity of GaN make it ideal for withstanding high electric fields and supporting large currents. The vertical topology of the CAVET allows for more efficient die area utilization, breakdown scaling with the height of the device, and burying high electric fields in the bulk where they will not charge interface states that can lead to current collapse at higher frequency.
Though GaN CAVETs are promising new devices, they are expensive to develop due to new or exotic materials and processing steps. As a result, the accurate simulation of GaN CAVETs has become critical to the development of new devices. Using Silvaco Atlas 5.24.1.R, best practices were developed for GaN CAVET simulation by recreating the structure and results of the pGaN insulated gate CAVET presented in chapter 3 of [8].
From the results it was concluded that the best simulation setup for transfer characteristics, output characteristics, and breakdown included the following. For methods, the use of Gummel, Block, Newton, and Trap. For models, SRH, Fermi, Auger, and impact selb. For mobility, the use of GANSAT and manually specified saturation velocity and mobility (based on doping concentration). Additionally, parametric sweeps showed that, of those tested, critical CAVET parameters included channel mobility (and thus doping), channel thickness, Current Blocking Layer (CBL) doping, gate overlap, and aperture width in rectangular devices or diameter in cylindrical devices.
Though GaN CAVETs are promising new devices, they are expensive to develop due to new or exotic materials and processing steps. As a result, the accurate simulation of GaN CAVETs has become critical to the development of new devices. Using Silvaco Atlas 5.24.1.R, best practices were developed for GaN CAVET simulation by recreating the structure and results of the pGaN insulated gate CAVET presented in chapter 3 of [8].
From the results it was concluded that the best simulation setup for transfer characteristics, output characteristics, and breakdown included the following. For methods, the use of Gummel, Block, Newton, and Trap. For models, SRH, Fermi, Auger, and impact selb. For mobility, the use of GANSAT and manually specified saturation velocity and mobility (based on doping concentration). Additionally, parametric sweeps showed that, of those tested, critical CAVET parameters included channel mobility (and thus doping), channel thickness, Current Blocking Layer (CBL) doping, gate overlap, and aperture width in rectangular devices or diameter in cylindrical devices.
ContributorsWarren, Andrew (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Zhao, Yuji (Committee member) / Arizona State University (Publisher)
Created2019
Description
Gallium Nitride (GaN) based microelectronics technology is a fast growing and most exciting semiconductor technology in the fields of high power and high frequency electronics. Excellent electrical properties of GaN such as high carrier concentration and high carrier motility makes GaN based high electron mobility transistors (HEMTs) a preferred choice for RF applications. However, a very high temperature in the active region of the GaN HEMT leads to a significant degradation of the device performance by effecting carrier mobility and concentration. Thus, thermal management in GaN HEMT in an effective manner is key to this technology to reach its full potential.
In this thesis, an electro-thermal model of an AlGaN/GaN HEMT on a SiC substrate is simulated using Silvaco (Atlas) TCAD tools. Output characteristics, current density and heat flow at the GaN-SiC interface are key areas of analysis in this work. The electrical characteristics show a sharp drop in drain currents for higher drain voltages. Temperature profile across the device is observed. At the interface of GaN-SiC, there is a sharp drop in temperature indicating a thermal resistance at this interface. Adding to the existing heat in the device, this difference heat is reflected back into the device, further increasing the temperatures in the active region. Structural changes such as GaN micropits, were introduced at the GaN-SiC interface along the length of the device, to make the heat flow smooth rather than discontinuous. With changing dimensions of these micropits, various combinations were tried to reduce the temperature and enhance the device performance. These GaN micropits gave effective results by reducing heat in active region, by spreading out the heat on to the sides of the device rather than just concentrating right below the hot spot. It also helped by allowing a smooth flow of heat at the GaN-SiC interface. There was an increased peak current density in the active region of the device contributing to improved electrical characteristics. In the end, importance of thermal management in these high temperature devices is discussed along with future prospects and a conclusion of this thesis.
In this thesis, an electro-thermal model of an AlGaN/GaN HEMT on a SiC substrate is simulated using Silvaco (Atlas) TCAD tools. Output characteristics, current density and heat flow at the GaN-SiC interface are key areas of analysis in this work. The electrical characteristics show a sharp drop in drain currents for higher drain voltages. Temperature profile across the device is observed. At the interface of GaN-SiC, there is a sharp drop in temperature indicating a thermal resistance at this interface. Adding to the existing heat in the device, this difference heat is reflected back into the device, further increasing the temperatures in the active region. Structural changes such as GaN micropits, were introduced at the GaN-SiC interface along the length of the device, to make the heat flow smooth rather than discontinuous. With changing dimensions of these micropits, various combinations were tried to reduce the temperature and enhance the device performance. These GaN micropits gave effective results by reducing heat in active region, by spreading out the heat on to the sides of the device rather than just concentrating right below the hot spot. It also helped by allowing a smooth flow of heat at the GaN-SiC interface. There was an increased peak current density in the active region of the device contributing to improved electrical characteristics. In the end, importance of thermal management in these high temperature devices is discussed along with future prospects and a conclusion of this thesis.
ContributorsSuri, Suraj (Author) / Zhao, Yuji (Thesis advisor) / Vasileska, Dragika (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2016
Description
This work analyzes and develops a point-of-load (PoL) synchronous buck converter using enhancement-mode Gallium Nitride (e-GaN), with emphasis on optimizing reverse conduction loss by using a well-known technique of placing an anti-parallel Schottky diode across the synchronous power device. This work develops an improved analytical switching model for the GaN-based converter with the Schottky diode using piecewise linear approximations.
To avoid a shoot-through between the power switches of the buck converter, a small dead-time is inserted between gate drive switching transitions. Despite optimum dead-time management for a power converter, optimum dead-times vary for different load conditions. These variations become considerably large for PoL applications, which demand high output current with low output voltages. At high switching frequencies, these variations translate into losses that contribute significantly to the total loss of the converter. To understand and quantify power loss in a hard-switching buck converter that uses a GaN power device in parallel with a Schottky diode, piecewise transitions are used to develop an analytical switching model that quantifies the contribution of reverse conduction loss of GaN during dead-time.
The effects of parasitic elements on the dynamics of the switching converter are investigated during one switching cycle of the converter. A designed prototype of a buck converter is correlated to the predicted model to determine the accuracy of the model. This comparison is presented using simulations and measurements at 400 kHz and 2 MHz converter switching speeds for load (1A) condition and fixed dead-time values. Furthermore, performance of the buck converter with and without the Schottky diode is also measured and compared to demonstrate and quantify the enhanced performance when using an anti-parallel diode. The developed power converter achieves peak efficiencies of 91.7% and 93.86% for 2 MHz and 400 KHz switching frequencies, respectively, and drives load currents up to 6A for a voltage conversion from 12V input to 3.3V output.
In addition, various industry Schottky diodes have been categorized based on their packaging and electrical characteristics and the developed analytical model provides analytical expressions relating the diode characteristics to power stage performance parameters. The performance of these diodes has been characterized for different buck converter voltage step-down ratios that are typically used in industry applications and different switching frequencies ranging from 400 KHz to 2 MHz.
To avoid a shoot-through between the power switches of the buck converter, a small dead-time is inserted between gate drive switching transitions. Despite optimum dead-time management for a power converter, optimum dead-times vary for different load conditions. These variations become considerably large for PoL applications, which demand high output current with low output voltages. At high switching frequencies, these variations translate into losses that contribute significantly to the total loss of the converter. To understand and quantify power loss in a hard-switching buck converter that uses a GaN power device in parallel with a Schottky diode, piecewise transitions are used to develop an analytical switching model that quantifies the contribution of reverse conduction loss of GaN during dead-time.
The effects of parasitic elements on the dynamics of the switching converter are investigated during one switching cycle of the converter. A designed prototype of a buck converter is correlated to the predicted model to determine the accuracy of the model. This comparison is presented using simulations and measurements at 400 kHz and 2 MHz converter switching speeds for load (1A) condition and fixed dead-time values. Furthermore, performance of the buck converter with and without the Schottky diode is also measured and compared to demonstrate and quantify the enhanced performance when using an anti-parallel diode. The developed power converter achieves peak efficiencies of 91.7% and 93.86% for 2 MHz and 400 KHz switching frequencies, respectively, and drives load currents up to 6A for a voltage conversion from 12V input to 3.3V output.
In addition, various industry Schottky diodes have been categorized based on their packaging and electrical characteristics and the developed analytical model provides analytical expressions relating the diode characteristics to power stage performance parameters. The performance of these diodes has been characterized for different buck converter voltage step-down ratios that are typically used in industry applications and different switching frequencies ranging from 400 KHz to 2 MHz.
ContributorsKoli, Gauri (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2020