Matching Items (11)
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- All Subjects: RRAM
- All Subjects: Sensors
- All Subjects: controls
- Creators: Electrical Engineering Program
- Member of: Barrett, The Honors College Thesis/Creative Project Collection
- Resource Type: Text
Description
This project details a magnetic field detection system that can be mounted on an unmanned aerial vehicle (UAV). The system is comprised of analog circuitry to detect and process the magnetic signals, digital circuitry to sample and store the data outputted from the analog front end, and finally a UAV to carry and mobilize the electronic parts. The system should be able to sense magnetic fields from power transmission lines, enabling the determination of whether or not current is running through the power line.
ContributorsTheoharatos, Dimitrios (Co-author) / Brazones, Ryan (Co-author) / Pagaduan, Patrick (Co-author) / Allee, David (Thesis director) / Karady, George (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2015-05
Description
Active pixel sensors hold a lot of promise for space applications in star tracking because of their effectiveness against radiation, small size, and on-chip processing. The research focus is on documenting and validating ground test equipment for these types of sensors. Through demonstrating the utility of a commercial sensor, the research will be able to work on ensuring the accuracy of ground tests. This contribution allows for future research on improving active pixel sensor performance.
ContributorsDotson, Breydan Lane (Author) / White, Daniel (Thesis director) / Jansen, Rolf (Committee member) / Mechanical and Aerospace Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
Description
This paper summarizes the [1] ideas behind, [2] needs, [3] development, and [4] testing of 3D-printed sensor-stents known as Stentzors. This sensor was successfully developed entirely from scratch, tested, and was found to have an output of 3.2*10-6 volts per RMS pressure in pascals. This paper also recommends further work to render the Stentzor deployable in live subjects, including [1] further design optimization, [2] electrical isolation, [3] wireless data transmission, and [4] testing for aneurysm prevention.
ContributorsMeidinger, Aaron Michael (Author) / LaBelle, Jeffrey (Thesis director) / Frakes, David (Committee member) / Barrett, The Honors College (Contributor) / Mechanical and Aerospace Engineering Program (Contributor)
Created2014-05
Description
Resistive Random Access Memory (RRAM) is an emerging type of non-volatile memory technology that seeks to replace FLASH memory. The RRAM crossbar array is advantageous in its relatively small cell area and faster read latency in comparison to NAND and NOR FLASH memory; however, the crossbar array faces design challenges of its own in sneak-path currents that prevent proper reading of memory stored in the RRAM cell. The Current Sensing Amplifier is one method of reading RRAM crossbar arrays. HSpice simulations are used to find the associated reading delays of the Current Sensing Amplifier with respect to various sizes of RRAM crossbar arrays, as well as the largest array size compatible for accurate reading. It is found that up to 1024x1024 arrays are achievable with a worst-case read delay of 815ps, and it is further likely 2048x2048 arrays are able to be read using the Current Sensing Amplifier. In comparing the Current Sensing Amplifier latency results with previously obtained latency results from the Voltage Sensing Amplifier, it is shown that the Voltage Sensing Amplifier reads arrays in sizes up to 256x256 faster while the Current Sensing Amplifier reads larger arrays faster.
ContributorsMoore, Jenna Barber (Author) / Yu, Shimeng (Thesis director) / Liu, Rui (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-12
Description
This thesis outlines the hand-held memory characterization testing system that is to be created into a PCB (printed circuit board). The circuit is designed to apply voltages diagonally through a RRAM cell (32x32 memory array). The purpose of this sweep across the RRAM is to measure and calculate the high and low resistance state value over a specified amount of testing cycles. With each cell having a unique output of high and low resistance states a unique characterization of each RRAM cell is able to be developed. Once the memory is characterized, the specific RRAM cell that was tested is then able to be used in a varying amount of applications for different things based on its uniqueness. Due to an inability to procure a packaged RRAM cell, a Mock-RRAM was instead designed in order to emulate the same behavior found in a RRAM cell.
The final testing circuit and Mock-RRAM are varied and complex but come together to be able to produce a measured value of the high resistance and low resistance state. This is done by the Arduino autonomously digitizing the anode voltage, cathode voltage, and output voltage. A ramp voltage that sweeps from 1V to -1V is applied to the Mock-RRAM acting as an input. This ramp voltage is then later defined as the anode voltage which is just one of the two nodes connected to the Mock-RRAM. The cathode voltage is defined as the other node at which the voltage drops across the Mock-RRAM. Using these three voltages as input to the Arduino, the Mock-RRAM path resistance is able to be calculated at any given point in time. Conducting many test cycles and calculating the high and low resistance values allows for a graph to be developed of the chaotic variation of resistance state values over time. This chaotic variation can then be analyzed further in the future in order to better predict trends and characterize the RRAM cell that was tested.
Furthermore, the interchangeability of many devices on the PCB allows for the testing system to do more in the future. Ports have been added to the final PCB in order to connect a packaged RRAM cell. This will allow for the characterization of a real RRAM memory cell later down the line rather than a Mock-RRAM as emulation. Due to the autonomous testing, very few human intervention is needed which makes this board a great baseline for others in the future looking to add to it and collect larger pools of data.
The final testing circuit and Mock-RRAM are varied and complex but come together to be able to produce a measured value of the high resistance and low resistance state. This is done by the Arduino autonomously digitizing the anode voltage, cathode voltage, and output voltage. A ramp voltage that sweeps from 1V to -1V is applied to the Mock-RRAM acting as an input. This ramp voltage is then later defined as the anode voltage which is just one of the two nodes connected to the Mock-RRAM. The cathode voltage is defined as the other node at which the voltage drops across the Mock-RRAM. Using these three voltages as input to the Arduino, the Mock-RRAM path resistance is able to be calculated at any given point in time. Conducting many test cycles and calculating the high and low resistance values allows for a graph to be developed of the chaotic variation of resistance state values over time. This chaotic variation can then be analyzed further in the future in order to better predict trends and characterize the RRAM cell that was tested.
Furthermore, the interchangeability of many devices on the PCB allows for the testing system to do more in the future. Ports have been added to the final PCB in order to connect a packaged RRAM cell. This will allow for the characterization of a real RRAM memory cell later down the line rather than a Mock-RRAM as emulation. Due to the autonomous testing, very few human intervention is needed which makes this board a great baseline for others in the future looking to add to it and collect larger pools of data.
ContributorsDobrin, Ryan Christopher (Co-author) / Halden, Matthew (Co-author) / Hall, Tanner (Co-author) / Barnaby, Hugh (Thesis director) / Kitchen, Jennifer (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2019-05
Description
RRAM is an emerging technology that looks to replace FLASH NOR and possibly NAND memory. It is attractive because it uses an adjustable resistance and does not rely on charge; in the sub-10nm feature size circuitry this is critical. However, RRAM cross-point arrays suffer tremendously from leakage currents that prevent proper readings in larger array sizes. In this research an exponential IV selector was added to each cell to minimize this current. Using this technique the largest array-size supportable was determined to be 512x512 cells using the conventional voltage sense amplifier by HSPICE simulations. However, with the increase in array size, the sensing latency also remarkably increases due to more sneak path currents, approaching 873 ns for the 512x512 array.
ContributorsMadler, Ryan Anton (Author) / Yu, Shimeng (Thesis director) / Cao, Yu (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05
Description
The team has designed and built a golf swing analyzer that informs the user of his mistakes while putting with a golf club. The team also interfaced a Linux program with the analyzer that allows the user to review the flaws in his golf swing. In addition, the application is more personalized than existing devices and tailored to the individual based on his level of experience. The analyzer consists of an accelerometer, gyroscope, magnetometer, vibration motor, and microcontroller that are connected on a board that attaches to the top of the shaft of a golf club, fitting inside a 3D printed case. The team has assembled all of the necessary hardware, and is able to successfully display critical parameters of a golf putt, as well as send instant feedback to the user. The final budget for this project was $378.24
ContributorsKaur, Hansneet (Co-author) / Cox, Jeremy (Co-author) / Farnsworth, Chad (Co-author) / Zorob, Nabil (Co-author) / Chae, Junseok (Thesis director) / Aberle, James (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2015-12
Description
This project examines the dynamics and design of control systems for a rocket in propulsive ascent and descent using a simplified model with motion constrained to a vertical plane. The governing differential equations are analyzed. They are then linearized, after which transfer functions are derived relating controllable input variables to controlled output variables. The effect of changes in various parameters as well as other aspects of the system are examined. Methods for controller design based on the derived transfer functions are discussed. This will include the discussion of control of the final descent and landing of the rocket. Lastly, there is a brief discussion about both the successes and limitations of the model analyzed.
ContributorsWarner, Adin (Author) / Rodriguez, Armando (Thesis director) / Shafique, Ashfaque (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2021-12
Description
The focus of this project investigates high mobility robotics by developing a fully integrated framework for a ball-balancing robot. Using Lagrangian mechanics, a model for the robot was derived and used to conduct trade studies on significant system parameters. With a broad understanding of system dynamics, controllers were designed using LQR methodology. A prototype was then built and tested to exhibit desired reference command following and disturbance attenuation.
ContributorsKapron, Mark Andrew (Author) / Rodriguez, Armando (Thesis director) / Artemiadis, Panagiotis (Committee member) / Industrial, Systems & Operations Engineering Prgm (Contributor) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2019-05
Description
Most machine learning algorithms, and specifically neural networks, utilize vector-matrix multiplication (VMM) to process information, but these calculations are CPU intensive and can have long run-times. This issue is fundamentally outlined by the von Neumann bottleneck. Because of this undesirable expense associated with performing VMM via software, the exploration of new ways to perform the same calculations via hardware have grown more popular. When performed with hardware that is specialized to perform these calculations, VMM becomes far more power-efficient and less time consuming. This project expands upon those principles and seeks to validate the use of RRAM in this hardware.
The flexibility of the conductance of RRAM makes these devices a strong contender for hardware-driven VMM calculation for neural network computing. The conductance of these devices is affected by the pulse width of a voltage signal sent across the devices at each node. This pulse is produced on-chip and can be modified by user inputs. The design of this pulse- producing circuit, as well as the simulated and physical functionality of the design, is discussed in this Honors Thesis.
Simulation and physical testing of the pulse-producing design on the ASIC have verified correct operation of the design. This operation is imperative to the future ability of the ASIC to perform accurate VMM.
ContributorsPearson, Katherine (Author) / Barnaby, Hugh (Thesis director) / Wilson, Donald (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor) / School of International Letters and Cultures (Contributor)
Created2022-05