Matching Items (6)
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- All Subjects: Memory
- Creators: Conrad, Cheryl
Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
This thesis outlines the hand-held memory characterization testing system that is to be created into a PCB (printed circuit board). The circuit is designed to apply voltages diagonally through a RRAM cell (32x32 memory array). The purpose of this sweep across the RRAM is to measure and calculate the high and low resistance state value over a specified amount of testing cycles. With each cell having a unique output of high and low resistance states a unique characterization of each RRAM cell is able to be developed. Once the memory is characterized, the specific RRAM cell that was tested is then able to be used in a varying amount of applications for different things based on its uniqueness. Due to an inability to procure a packaged RRAM cell, a Mock-RRAM was instead designed in order to emulate the same behavior found in a RRAM cell.
The final testing circuit and Mock-RRAM are varied and complex but come together to be able to produce a measured value of the high resistance and low resistance state. This is done by the Arduino autonomously digitizing the anode voltage, cathode voltage, and output voltage. A ramp voltage that sweeps from 1V to -1V is applied to the Mock-RRAM acting as an input. This ramp voltage is then later defined as the anode voltage which is just one of the two nodes connected to the Mock-RRAM. The cathode voltage is defined as the other node at which the voltage drops across the Mock-RRAM. Using these three voltages as input to the Arduino, the Mock-RRAM path resistance is able to be calculated at any given point in time. Conducting many test cycles and calculating the high and low resistance values allows for a graph to be developed of the chaotic variation of resistance state values over time. This chaotic variation can then be analyzed further in the future in order to better predict trends and characterize the RRAM cell that was tested.
Furthermore, the interchangeability of many devices on the PCB allows for the testing system to do more in the future. Ports have been added to the final PCB in order to connect a packaged RRAM cell. This will allow for the characterization of a real RRAM memory cell later down the line rather than a Mock-RRAM as emulation. Due to the autonomous testing, very few human intervention is needed which makes this board a great baseline for others in the future looking to add to it and collect larger pools of data.
The final testing circuit and Mock-RRAM are varied and complex but come together to be able to produce a measured value of the high resistance and low resistance state. This is done by the Arduino autonomously digitizing the anode voltage, cathode voltage, and output voltage. A ramp voltage that sweeps from 1V to -1V is applied to the Mock-RRAM acting as an input. This ramp voltage is then later defined as the anode voltage which is just one of the two nodes connected to the Mock-RRAM. The cathode voltage is defined as the other node at which the voltage drops across the Mock-RRAM. Using these three voltages as input to the Arduino, the Mock-RRAM path resistance is able to be calculated at any given point in time. Conducting many test cycles and calculating the high and low resistance values allows for a graph to be developed of the chaotic variation of resistance state values over time. This chaotic variation can then be analyzed further in the future in order to better predict trends and characterize the RRAM cell that was tested.
Furthermore, the interchangeability of many devices on the PCB allows for the testing system to do more in the future. Ports have been added to the final PCB in order to connect a packaged RRAM cell. This will allow for the characterization of a real RRAM memory cell later down the line rather than a Mock-RRAM as emulation. Due to the autonomous testing, very few human intervention is needed which makes this board a great baseline for others in the future looking to add to it and collect larger pools of data.
ContributorsDobrin, Ryan Christopher (Co-author) / Halden, Matthew (Co-author) / Hall, Tanner (Co-author) / Barnaby, Hugh (Thesis director) / Kitchen, Jennifer (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2019-05
Description
The aim of this study was to determine whether IUD administration, with and without the presence of Levo, and with and without the presence of the ovaries, impacts cognition in a rat model. Rats received either Sham or Ovariectomy (Ovx) surgery (removal of the ovaries), plus either no IUD, a Blank IUD (without Levo), or a Levo-releasing IUD (Levo IUD), enabling us to evaluate the effects of Ovx and the effects of IUD administration on cognition. Two weeks after surgery, all treatment groups were tested on the water radial arm maze, Morris water maze, and visible platform task to evaluate cognition. At sacrifice, upon investigation of the uteri, it was determined that some of the IUDs were no longer present in animals from these groups: Sham\u2014Blank IUD, Ovx\u2014Blank IUD, and Sham\u2014Levo IUD. Results from the remaining three groups showed that compared to Sham animals with no IUDs, Ovx animals with no IUDs had marginally impaired working memory performance, and that Ovx animals with Levo IUDs as compared to Ovx animals with no IUDs had marginally enhanced memory performance, not specific to a particular memory type. Results also showed that Ovx animals with Levo IUDs had qualitatively more cells in their vaginal smears and increased uterine horn weight compared to Ovx animals with no IUDs, suggesting local stimulation of the Levo IUDs to the uterine horns. Overall, these results provide alternative evidence to the hypothesis that the Levo IUD administers Levo in solely a localized manner, and suggests that the possibility for the Levo IUD to affect reproductive cyclicity in ovary-intact animals is not rejected. The potential for the Levo IUD to exert effects on cognition suggests that either the hormone does in fact systemically circulate, or that the Levo IUD administration affects cognition by altering an as yet undetermined hormonal or other feedback between the uterus and the brain.
ContributorsStrouse, Isabel Martha (Author) / Bimonte-Nelson, Heather (Thesis director) / Glenberg, Arthur (Committee member) / Sirianni, Rachael (Committee member) / Conrad, Cheryl (Committee member) / School of Life Sciences (Contributor) / Department of Psychology (Contributor) / Barrett, The Honors College (Contributor)
Created2018-12
Description
Estradiol (E2) and Levonorgestrel (Levo) are two hormones commonly used in hormone therapy (HT) to decrease symptoms associated with menopause. Both of these hormones have been shown to have beneficial effects on cognition when given alone in a rodent model of menopause. However, it is unknown whether these hormones, when taken in combination, are beneficial or harmful to cognition. This is a critically important question given that these hormones are most often given in combination versus separately. This thesis is composed of two studies examining the cognitive effects of E2 and Levo using a rat model of surgical menopause. Study 1 assessed how the dose of E2 treatment in rats impacted cognitive performance, and found that low dose E2 enhanced working memory performance. Next, based on the results from Study 1, Study 2 used low dose E2 in combination with different doses of Levo to examine the cognitive effects of several E2 to Levo ratio combinations. The results from Study 2 demonstrated that the combination of low dose E2 with a high dose of Levo at a 1:2 ratio impaired cognition, and that the ratio currently used in HT, 3:1, may also negatively impact cognition. Indeed, there was a dose response effect indicating that working and reference memory performance was incrementally impaired as Levo dose increased. The findings in this thesis suggest that the E2 plus Levo combination is likely not neutral for cognitive function, and prompts further evaluation in menopausal women, as well as drug discovery research to optimize HT using highly controlled preclinical models.
ContributorsBerns-Leone, Claire Elizabeth (Co-author) / Prakapenka, Alesia (Co-author) / Pena, Veronica (Co-author) / Northup-Smith, Steven (Co-author) / Melikian, Ryan (Co-author) / Ladwig, Ducileia (Co-author) / Patel, Shruti (Co-author) / Croft, Corissa (Co-author) / Bimonte-Nelson, Heather (Thesis director) / Glenberg, Arthur (Committee member) / Conrad, Cheryl (Committee member) / School of Life Sciences (Contributor) / Department of Psychology (Contributor) / Barrett, The Honors College (Contributor)
Created2016-12
Description
Readout Integrated Circuits(ROICs) are important components of infrared(IR) imag
ing systems. Performance of ROICs affect the quality of images obtained from IR
imaging systems. Contemporary infrared imaging applications demand ROICs that
can support large dynamic range, high frame rate, high output data rate, at low
cost, size and power. Some of these applications are military surveillance, remote
sensing in space and earth science missions and medical diagnosis. This work focuses
on developing a ROIC unit cell prototype for National Aeronautics and Space Ad
ministration(NASA), Jet Propulsion Laboratory’s(JPL’s) space applications. These
space applications also demand high sensitivity, longer integration times(large well
capacity), wide operating temperature range, wide input current range and immunity
to radiation events such as Single Event Latchup(SEL).
This work proposes a digital ROIC(DROIC) unit cell prototype of 30ux30u size,
to be used mainly with NASA JPL’s High Operating Temperature Barrier Infrared
Detectors(HOT BIRDs). Current state of the art DROICs achieve a dynamic range
of 16 bits using advanced 65-90nm CMOS processes which adds a lot of cost overhead.
The DROIC pixel proposed in this work uses a low cost 180nm CMOS process and
supports a dynamic range of 20 bits operating at a low frame rate of 100 frames per
second(fps), and a dynamic range of 12 bits operating at a high frame rate of 5kfps.
The total electron well capacity of this DROIC pixel is 1.27 billion electrons, enabling
integration times as long as 10ms, to achieve better dynamic range. The DROIC unit
cell uses an in-pixel 12-bit coarse ADC and an external 8-bit DAC based fine ADC.
The proposed DROIC uses layout techniques that make it immune to radiation up to
300krad(Si) of total ionizing dose(TID) and single event latch-up(SEL). It also has a
wide input current range from 10pA to 1uA and supports detectors operating from
Short-wave infrared (SWIR) to longwave infrared (LWIR) regions.
ing systems. Performance of ROICs affect the quality of images obtained from IR
imaging systems. Contemporary infrared imaging applications demand ROICs that
can support large dynamic range, high frame rate, high output data rate, at low
cost, size and power. Some of these applications are military surveillance, remote
sensing in space and earth science missions and medical diagnosis. This work focuses
on developing a ROIC unit cell prototype for National Aeronautics and Space Ad
ministration(NASA), Jet Propulsion Laboratory’s(JPL’s) space applications. These
space applications also demand high sensitivity, longer integration times(large well
capacity), wide operating temperature range, wide input current range and immunity
to radiation events such as Single Event Latchup(SEL).
This work proposes a digital ROIC(DROIC) unit cell prototype of 30ux30u size,
to be used mainly with NASA JPL’s High Operating Temperature Barrier Infrared
Detectors(HOT BIRDs). Current state of the art DROICs achieve a dynamic range
of 16 bits using advanced 65-90nm CMOS processes which adds a lot of cost overhead.
The DROIC pixel proposed in this work uses a low cost 180nm CMOS process and
supports a dynamic range of 20 bits operating at a low frame rate of 100 frames per
second(fps), and a dynamic range of 12 bits operating at a high frame rate of 5kfps.
The total electron well capacity of this DROIC pixel is 1.27 billion electrons, enabling
integration times as long as 10ms, to achieve better dynamic range. The DROIC unit
cell uses an in-pixel 12-bit coarse ADC and an external 8-bit DAC based fine ADC.
The proposed DROIC uses layout techniques that make it immune to radiation up to
300krad(Si) of total ionizing dose(TID) and single event latch-up(SEL). It also has a
wide input current range from 10pA to 1uA and supports detectors operating from
Short-wave infrared (SWIR) to longwave infrared (LWIR) regions.
ContributorsPraveen, Subramanya Chilukuri (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Long, Yu (Committee member) / Arizona State University (Publisher)
Created2019
Description
Progestogens, such as progesterone (P4), medroxyprogesterone acetate (MPA), and micronized progesterone (mP4), are given to ovary-intact women during the transition to menopause to attenuate heavy uterine bleeding and other symptoms. Both progesterone and MPA administration have been shown to impair cognition in ovariectomized (Ovx) rats compared to vehicle-treated controls. mP4, however, has yet to be investigated for cognitive effects in a preclinical setting. Further, progestogens affect the GABA (-aminobutyric acid) ergic system, specifically glutamic acid decarboxylase (GAD) the rate limiting enzyme necessary for synthesizing GABA. The goal of this experiment was to investigate the cognitive impact of P4, MPA, and mP4, in an ovary-intact transitional menopause model using 4-vinylcyclohexene diepoxide (VCD) and assess whether these potential changes were related to the GABAergic system. One group of rats received vehicle injections, and the remainder of the groups received VCD to induce follicular depletion, modeling transitional menopause in women. Vehicle or hormone administration began during perimenopause to model the time period when women often take progestogens alone. Rats then underwent testing to assess spatial working and reference memory in the water radial-arm maze (WRAM) and spatial reference memory in the Morris water maze (MWM). Results indicate that P4 and MPA improved learning for working memory measure, but only MPA impaired memory retention in the WRAM. For the WRAM reference memory measure, VCD only treated rats showed impaired learning and memory retention compared to vehicle controls; progestogens did not impact this impairment. Although GAD expression did not differ between treatment groups, in general, there was a relationship between GAD expression and WRAM performance such that rats that tended to have higher GAD levels also tended to make more WRAM working memory errors. Thus, while P4 and MPA have been previously shown to impair cognition in an Ovx model, giving these hormones early in an ovary-intact perimenopause model elicits divergent effects, such that these progestogens can improve cognition. Additionally, these findings suggest that the cognitive changes seen herein are related to the interaction between progestogens and the GABAergic system. Further investigation into progestogens is warranted to fully understand their impact on cognition given the importance of utilizing progestogens in the clinic.
ContributorsPena, Veronica Leigh (Author) / Bimonte-Nelson, Heather A. (Thesis advisor) / Conrad, Cheryl (Committee member) / Gipson-Reichardt, Cassandra (Committee member) / Arizona State University (Publisher)
Created2019