Matching Items (5)
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- All Subjects: Memory
- Creators: Brewer, Gene A.
- Creators: Kitchen, Jennifer
- Member of: ASU Electronic Theses and Dissertations
Description
Current theoretical debate, crossing the bounds of memory theory and mental imagery, surrounds the role of eye movements in successful encoding and retrieval. Although the eyes have been shown to revisit previously-viewed locations during retrieval, the functional role of these saccades is not known. Understanding the potential role of eye movements may help address classic questions in recognition memory. Specifically, are episodic traces rich and detailed, characterized by a single strength-driven recognition process, or are they better described by two separate processes, one for vague information and one for the retrieval of detail? Three experiments are reported, in which participants encoded audio-visual information while completing controlled patterns of eye movements. By presenting information in four sources (i.e., voices), assessments of specific and partial source memory were measured at retrieval. Across experiments, participants' eye movements at test were manipulated. Experiment 1 allowed free viewing, Experiment 2 required externally-cued fixations to previously-relevant (or irrelevant) screen locations, and Experiment 3 required externally-cued new or familiar oculomotor patterns to multiple screen locations in succession. Although eye movements were spontaneously reinstated when gaze was unconstrained during retrieval (Experiment 1), externally-cueing participants to re-engage in fixations or oculomotor patterns from encoding (Experiments 2 and 3) did not enhance retrieval. Across all experiments, participants' memories were well-described by signal-detection models of memory. Source retrieval was characterized by a continuous process, with evidence that source retrieval occurred following item memory failures, and additional evidence that participants partially recollected source, in the absence of specific item retrieval. Pupillometry provided an unbiased metric by which to compute receiver operating characteristic (ROC) curves, which were consistently curvilinear (but linear in z-space), supporting signal-detection predictions over those from dual-process theories. Implications for theoretical views of memory representations are discussed.
ContributorsPapesh, Megan H (Author) / Goldinger, Stephen D (Thesis advisor) / Brewer, Gene A. (Committee member) / Reichle, Erik D. (Committee member) / Homa, Donald (Committee member) / Glenberg, Arthur M. (Committee member) / Arizona State University (Publisher)
Created2012
Description
The present study examined the effect of value-directed encoding on recognition memory and how various divided attention tasks at encoding alter value-directed remembering. In the first experiment, participants encoded words that were assigned either high or low point values in multiple study-test phases. The points corresponded to the value the participants could earn by successfully recognizing the words in an upcoming recognition memory task. Importantly, participants were instructed that their goal was to maximize their score in this memory task. The second experiment was modified such that while studying the words participants simultaneously completed a divided attention task (either articulatory suppression or random number generation). The third experiment used a non-verbal tone detection divided attention task (easy or difficult versions). Subjective states of recollection (i.e., “Remember”) and familiarity (i.e., “Know”) were assessed at retrieval in all experiments. In Experiment 1, high value words were recognized more effectively than low value words, and this difference was primarily driven by increases in “Remember” responses with no difference in “Know” responses. In Experiment 2, the pattern of subjective judgment results from the articulatory suppression condition replicated Experiment 1. However, in the random number generation condition, the effect of value on recognition memory was lost. This same pattern of results was found in Experiment 3 which implemented a different variant of the divided attention task. Overall, these data suggest that executive processes are used when encoding valuable information and that value-directed improvements to memory are not merely the result of differential rehearsal.
ContributorsElliott, Blake L (Author) / Brewer, Gene A. (Thesis advisor) / McClure, Samuel M. (Committee member) / Fine, Justin M (Committee member) / Arizona State University (Publisher)
Created2019
Description
An emerging literature on the relation between memory and importance has shown that people are able to selectively remember information that is more, relative to less important. Researchers in this field have operationalized importance by assigning value to the different information that participants are asked to study and remember. In the present investigation I developed two experiments, using a slightly altered value-directed-remembering (VDR) paradigm, to investigate whether and how value modifies the dynamics of memory organization and search. Moreover, I asked participants to perform a surprise final free recall task in order to examine the effects of value in the recall dynamics of final free recall. In Experiment 1, I compared the recall dynamics of delayed and final free recall between a control and a value condition, in the latter of which numbers appeared next to words, in random order, denoting the value of remembering each word during recall. In Experiment 2, I manipulated the order of presentation of the values by adding an ascending and a descending condition where values were presented in either an ascending or a descending order, respectively. Overall, my results indicated that value affected several measures of delayed and final free recall, without, in most cases, taking away the serial position effects on those same measures.
ContributorsStefanidi, Aikaterini (Author) / Brewer, Gene A. (Thesis advisor) / Glenberg, Arthur (Committee member) / Goldinger, Stephen (Committee member) / Arizona State University (Publisher)
Created2015
Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
Readout Integrated Circuits(ROICs) are important components of infrared(IR) imag
ing systems. Performance of ROICs affect the quality of images obtained from IR
imaging systems. Contemporary infrared imaging applications demand ROICs that
can support large dynamic range, high frame rate, high output data rate, at low
cost, size and power. Some of these applications are military surveillance, remote
sensing in space and earth science missions and medical diagnosis. This work focuses
on developing a ROIC unit cell prototype for National Aeronautics and Space Ad
ministration(NASA), Jet Propulsion Laboratory’s(JPL’s) space applications. These
space applications also demand high sensitivity, longer integration times(large well
capacity), wide operating temperature range, wide input current range and immunity
to radiation events such as Single Event Latchup(SEL).
This work proposes a digital ROIC(DROIC) unit cell prototype of 30ux30u size,
to be used mainly with NASA JPL’s High Operating Temperature Barrier Infrared
Detectors(HOT BIRDs). Current state of the art DROICs achieve a dynamic range
of 16 bits using advanced 65-90nm CMOS processes which adds a lot of cost overhead.
The DROIC pixel proposed in this work uses a low cost 180nm CMOS process and
supports a dynamic range of 20 bits operating at a low frame rate of 100 frames per
second(fps), and a dynamic range of 12 bits operating at a high frame rate of 5kfps.
The total electron well capacity of this DROIC pixel is 1.27 billion electrons, enabling
integration times as long as 10ms, to achieve better dynamic range. The DROIC unit
cell uses an in-pixel 12-bit coarse ADC and an external 8-bit DAC based fine ADC.
The proposed DROIC uses layout techniques that make it immune to radiation up to
300krad(Si) of total ionizing dose(TID) and single event latch-up(SEL). It also has a
wide input current range from 10pA to 1uA and supports detectors operating from
Short-wave infrared (SWIR) to longwave infrared (LWIR) regions.
ing systems. Performance of ROICs affect the quality of images obtained from IR
imaging systems. Contemporary infrared imaging applications demand ROICs that
can support large dynamic range, high frame rate, high output data rate, at low
cost, size and power. Some of these applications are military surveillance, remote
sensing in space and earth science missions and medical diagnosis. This work focuses
on developing a ROIC unit cell prototype for National Aeronautics and Space Ad
ministration(NASA), Jet Propulsion Laboratory’s(JPL’s) space applications. These
space applications also demand high sensitivity, longer integration times(large well
capacity), wide operating temperature range, wide input current range and immunity
to radiation events such as Single Event Latchup(SEL).
This work proposes a digital ROIC(DROIC) unit cell prototype of 30ux30u size,
to be used mainly with NASA JPL’s High Operating Temperature Barrier Infrared
Detectors(HOT BIRDs). Current state of the art DROICs achieve a dynamic range
of 16 bits using advanced 65-90nm CMOS processes which adds a lot of cost overhead.
The DROIC pixel proposed in this work uses a low cost 180nm CMOS process and
supports a dynamic range of 20 bits operating at a low frame rate of 100 frames per
second(fps), and a dynamic range of 12 bits operating at a high frame rate of 5kfps.
The total electron well capacity of this DROIC pixel is 1.27 billion electrons, enabling
integration times as long as 10ms, to achieve better dynamic range. The DROIC unit
cell uses an in-pixel 12-bit coarse ADC and an external 8-bit DAC based fine ADC.
The proposed DROIC uses layout techniques that make it immune to radiation up to
300krad(Si) of total ionizing dose(TID) and single event latch-up(SEL). It also has a
wide input current range from 10pA to 1uA and supports detectors operating from
Short-wave infrared (SWIR) to longwave infrared (LWIR) regions.
ContributorsPraveen, Subramanya Chilukuri (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Long, Yu (Committee member) / Arizona State University (Publisher)
Created2019